From 7cf618fe02b2070c9caeef346cdfef1eeb43e11c Mon Sep 17 00:00:00 2001
From: PotatoMaxwell <yueqin@cuhk.edu.hk>
Date: Mon, 1 Jun 2026 09:19:44 +0800
Subject: [PATCH] Programm architecture simplified so that the EDA can now run
 individually without generation of .gds file

---
 GDS_SVG_GENERATION_LOGIC.md                   |  216 ++++
 INTRANET_DEPLOYMENT.md                        |   14 +
 PDK_TECHNOLOGY_XSECTION_LOADING.md            |  581 +++++++++
 README.md                                     |   16 +-
 ...EC_SiN400_1310_1p0dB_L635_A0_QY_202604.png |  Bin 13750 -> 0 bytes
 ...EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml |   41 -
 backend/__pycache__/database.cpython-39.pyc   |  Bin 5978 -> 5977 bytes
 .../__pycache__/gds_builder.cpython-39.pyc    |  Bin 11953 -> 2331 bytes
 backend/__pycache__/pdk_access.cpython-39.pyc |  Bin 2458 -> 2438 bytes
 .../routed_layout_preview.cpython-39.pyc      |  Bin 1699 -> 1621 bytes
 .../router_dependency.cpython-39.pyc          |  Bin 0 -> 2451 bytes
 .../technology_manifest.cpython-39.pyc        |  Bin 1536 -> 1516 bytes
 backend/gds_builder.py                        |  297 +----
 backend/layout_preview.py                     |  154 ---
 backend/pdk_registry.py                       |  132 --
 backend/routed_layout_preview.py              |    9 +-
 backend/router_dependency.py                  |   77 ++
 backend/server.py                             |   95 +-
 database/admin/layout/MZM_TX/MZM_TX.svg       |  956 --------------
 database/admin/layout/MZM_TX/MZM_TX.yml       |  102 --
 database/admin/layout/MZM_TX/Spliter_1x4.yml  |  192 ---
 database/admin/layout/MZM_TX/canvas_1.svg     |   69 --
 .../{MZM_TX => mxpic_project_1}/.project.json |    2 +-
 .../mxpic_project_1.svg}                      |  226 ++--
 .../mxpic_project_1/mxpic_project_1.yml       |   89 ++
 database/mxpic_data.db                        |  Bin 131072 -> 131072 bytes
 .../2026-05-31-required-mxpic-router-stack.md |  330 +++++
 ...026-06-01-pdk-root-technology-migration.md |   93 ++
 frontend/canvas.html                          |    3 +
 ...400_Si220_PIN_mod_1310_L1300_QY_202603.yml |   76 --
 ..._Si220_PIN_mod_1310_L1300_QY_202603_BB.svg |   34 -
 ...L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeA1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeA2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeA3_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeA3_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeA4_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeA5_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeA5_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeE1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeE2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeE3_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeE4_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeE4_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeG1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeG2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeG2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeG3_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeG4_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeG4_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeZ1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeZ2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeZ2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeZ3_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeZ4_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeZ4_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeR1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeR2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeT1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeT2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeT2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeT3_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeT4_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeT4_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeT5_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeV1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeV1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeV2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeW1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeW1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeW2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeW3_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeW3_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeW4_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeX1_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeX1_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeX2_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeX3_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeX3_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeX4_QY_v1_20260303_BB.svg |   48 -
 ...L3000_GSSG_TRAIL_TypeX5_QY_v1_20260303.yml |  113 --
 ...00_GSSG_TRAIL_TypeX5_QY_v1_20260303_BB.svg |   48 -
 .../INDC_200pH_SiNPP_QY_202604.yml            |   46 -
 .../INDC_200pH_SiNPP_QY_202604_BB.svg         |   22 -
 .../RFPAD_GSSG_P625_QY_202604.yml             |   76 --
 .../RFPAD_GSSG_P625_QY_202604_BB.svg          |   34 -
 ...s_ABCD_292_P125_250_W80_80_QY_20260324.yml | 1095 -----------------
 .../RES_30OHM_NPP_QY_202604.yml               |   76 --
 .../RES_30OHM_NPP_QY_202604_BB.svg            |   34 -
 .../RES_35OHM_NPP_QY_202604.yml               |   76 --
 .../RES_35OHM_NPP_QY_202604_BB.svg            |   34 -
 .../RES_40OHM_NPP_QY_202604.yml               |   76 --
 .../RES_40OHM_NPP_QY_202604_BB.svg            |   34 -
 .../RES_50OHM_NPP_QY_202604.yml               |   76 --
 .../RES_50OHM_NPP_QY_202604_BB.svg            |   34 -
 .../QC_MARKER_QY_202603.yml                   |  216 ----
 .../QC_MARKER_QY_202603_BB.svg                |   90 --
 .../Silterra_EMO1_Optihk_LOGO_QY.yml          |   36 -
 .../Silterra_EMO1_Optihk_LOGO_QY_BB.svg       |   18 -
 .../SiN_EUB_1310_H400_w2500_L45_QY_202604.yml |   46 -
 ...N_EUB_1310_H400_w2500_L45_QY_202604_BB.svg |   22 -
 .../SiN_EUB_1310_H400_w3000_L45_QY_202604.yml |   46 -
 ...N_EUB_1310_H400_w3000_L45_QY_202604_BB.svg |   22 -
 .../Si_EUB_1310_H220_w2000_L50_QY_202604.yml  |   46 -
 ...i_EUB_1310_H220_w2000_L50_QY_202604_BB.svg |   22 -
 ..._EUB_1310_H220_w380_2000_L50_QY_202604.yml |   46 -
 ...B_1310_H220_w380_2000_L50_QY_202604_BB.svg |   22 -
 ...DC_SiN400_99_1_1310_jyh_quantex_202603.yml |   53 -
 ...EC_SiN400_1310_0p5dB_L935_A0_QY_202604.yml |   41 -
 ...SiN400_1310_0p5dB_L935_A0_QY_202604_BB.svg |   20 -
 ...EC_SiN400_1310_0p5dB_L935_A8_QY_202604.yml |   41 -
 ...SiN400_1310_0p5dB_L935_A8_QY_202604_BB.svg |   20 -
 ...EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml |   41 -
 ...SiN400_1310_1p0dB_L635_A0_QY_202604_BB.svg |   20 -
 ...EC_SiN400_1310_1p0dB_L635_A8_QY_202604.yml |   41 -
 ...SiN400_1310_1p0dB_L635_A8_QY_202604_BB.svg |   20 -
 ...x2MMI_1310nm_TE_Silterra_202603_ZKY_v2.yml |   51 -
 ...MI_1310nm_TE_Silterra_202603_ZKY_v2_BB.svg |   24 -
 .../2x2MMI_1310nm_TE_Silterra_202603_ZKY.yml  |   56 -
 ...x2MMI_1310nm_TE_Silterra_202603_ZKY_BB.svg |   26 -
 ...310_Monitor_Si220_Ge500_NPN_XHN_202604.yml |   63 -
 ...G_TERM_SiN220_1310_w380_t150_QY_202606.yml |   41 -
 ...ERM_SiN220_1310_w380_t150_QY_202606_BB.svg |   20 -
 ...G_TERM_SiN400_1310_w700_t150_QY_202606.yml |   41 -
 ...ERM_SiN400_1310_w700_t150_QY_202606_BB.svg |   20 -
 .../Si_Strip_Rib_TRX_w380.yml                 |   46 -
 .../Si_Strip_Rib_TRX_w380_BB.svg              |   22 -
 ...150R_SiPPP_L500_100OHM_DUMMY_QY_202604.yml |   46 -
 ...R_SiPPP_L500_100OHM_DUMMY_QY_202604_BB.svg |   22 -
 .../HT_150R_SiPPP_L500_100OHM_QY_202604.yml   |   67 -
 ...HT_150R_SiPPP_L500_100OHM_QY_202604_BB.svg |   30 -
 .../HT_150R_TiN_L200_200OHM_QY_202604.yml     |   67 -
 .../HT_150R_TiN_L200_200OHM_QY_202604_BB.svg  |   30 -
 ...T_150R_TiN_L500_200OHM_DUMMY_QY_202604.yml |   46 -
 ...50R_TiN_L500_200OHM_DUMMY_QY_202604_BB.svg |   22 -
 .../VOA_Si220_1310_L1050_QY_202603.yml        |   66 -
 .../VOA_Si220_1310_L1050_QY_202603_BB.svg     |   30 -
 .../EMO1_2ML_CU_Al_RDL/technology.yml         |   80 --
 mxpic/PDKs/Silterra/directories.yaml          |   22 -
 tests/layout-backend-static.test.js           |  113 +-
 tests/layout-ui-wiring.test.js                |    5 +
 160 files changed, 1640 insertions(+), 11497 deletions(-)
 create mode 100644 GDS_SVG_GENERATION_LOGIC.md
 create mode 100644 PDK_TECHNOLOGY_XSECTION_LOADING.md
 delete mode 100644 backend/PDK_libs/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.png
 delete mode 100644 backend/PDK_libs/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml
 create mode 100644 backend/__pycache__/router_dependency.cpython-39.pyc
 delete mode 100644 backend/layout_preview.py
 delete mode 100644 backend/pdk_registry.py
 create mode 100644 backend/router_dependency.py
 delete mode 100644 database/admin/layout/MZM_TX/MZM_TX.svg
 delete mode 100644 database/admin/layout/MZM_TX/MZM_TX.yml
 delete mode 100644 database/admin/layout/MZM_TX/Spliter_1x4.yml
 delete mode 100644 database/admin/layout/MZM_TX/canvas_1.svg
 rename database/admin/layout/{MZM_TX => mxpic_project_1}/.project.json (62%)
 rename database/admin/layout/{MZM_TX/Spliter_1x4.svg => mxpic_project_1/mxpic_project_1.svg} (62%)
 create mode 100644 database/admin/layout/mxpic_project_1/mxpic_project_1.yml
 create mode 100644 docs/superpowers/plans/2026-05-31-required-mxpic-router-stack.md
 create mode 100644 docs/superpowers/plans/2026-06-01-pdk-root-technology-migration.md
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA3_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA3_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA5_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA5_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA5_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA5_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE4_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE4_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG2_QY_v1_20260303.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG2_QY_v1_20260303_BB.svg
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 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/2x2MMI_1310nm_TE_Silterra_202603_ZKY/2x2MMI_1310nm_TE_Silterra_202603_ZKY_BB.svg
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/photodetectors/PD_1310_Monitor_Si220_Ge500_NPN_XHN_202604/PD_1310_Monitor_Si220_Ge500_NPN_XHN_202604.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/terminations/WG_TERM_SiN220_1310_w380_t150_QY_202606/WG_TERM_SiN220_1310_w380_t150_QY_202606.yml
 delete mode 100644 mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/terminations/WG_TERM_SiN220_1310_w380_t150_QY_202606/WG_TERM_SiN220_1310_w380_t150_QY_202606_BB.svg
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diff --git a/GDS_SVG_GENERATION_LOGIC.md b/GDS_SVG_GENERATION_LOGIC.md
new file mode 100644
index 0000000..b1f106b
--- /dev/null
+++ b/GDS_SVG_GENERATION_LOGIC.md
@@ -0,0 +1,216 @@
+# GDS and SVG Generation Logic Path
+
+This document traces the current code path for generating saved layout YAML,
+layout preview SVG, and downloadable project GDS when the user clicks
+`Build Layout` or `Build GDS`.
+
+Line numbers refer to the files as currently checked in.
+
+## Build-Time Router Gate
+
+`python backend/server.py` -> `app.run` starts without importing
+`mxpic_router`, `mxpic_forge`, Nazca, or gdstk. Login, dashboard, canvas
+editing, YAML generation, PDK browsing, and project save without preview do not
+require the external build stack.
+
+Build actions validate the external stack on demand:
+
+- `Build GDS` -> `backend/gds_builder.py` -> `require_router_stack()`.
+- `Build Layout` SVG preview -> `backend/routed_layout_preview.py` ->
+  `require_router_stack(require_gdstk=True)`.
+
+Important functions:
+
+- `ensure_router_path` (`backend/router_dependency.py` line 23) adds the sibling
+  `../mxpic_router` checkout to `sys.path` when present.
+- `require_router_stack` (`backend/router_dependency.py` line 31) imports
+  `mxpic_router`, `nazca`, and the route backend used by `mxpic_router`.
+  `gdstk` is checked only when SVG preview generation requests it.
+
+## Generated Files
+
+- Saved cell YAML: `database/<username>/layout/<project>/<cell>.yml`
+  - Path helpers: `user_layout_root`, `project_root`, `cell_file_path`
+    (`backend/server.py` lines 124-137).
+- Saved layout preview SVG: `database/<username>/layout/<project>/<cell>.svg`
+  - Path helper: `cell_svg_path` (`backend/server.py` lines 140-142).
+- Optional route sidecar: `database/<username>/layout/<project>/<cell>.routes.yml`
+  - Path helper and writer: `cell_routes_path`, `write_route_points_sidecar`
+    (`backend/server.py` lines 145-175).
+- Downloadable GDS export: `database/_exports/<uuid>/<project>.gds`
+  - Created by `create_export_path` (`backend/pdk_access.py` lines 53-59).
+
+## Build Layout: Click Button -> YAML -> Router GDS -> SVG
+
+Compact path:
+
+`Click Build Layout` -> `handleBuildLayout` (`frontend/canvas.html` line 6209) :
+`buildYamlForPage` (`frontend/canvas.html` line 6141) generates layout YAML ->
+POST `/api/save-layout` (`frontend/canvas.html` line 6219) -> `save_layout`
+(`backend/server.py` line 715) writes `<cell>.yml` -> `create_routed_layout_svg`
+(`backend/server.py` line 734) -> `mxpic_router.build_project_gds` generates
+temporary Nazca GDS -> `gdstk.read_gds` + `write_svg` writes `<cell>.svg` ->
+backend returns `svg_url` -> `openLayoutPreview` (`frontend/canvas.html` line
+6183) opens the SVG preview tab.
+
+Detailed path:
+
+1. The button is rendered only for non-preview pages:
+   - `<button onClick={handleBuildLayout}>` (`frontend/canvas.html` lines
+     6491-6498).
+
+2. `handleBuildLayout` creates YAML for the active page:
+   - `handleBuildLayout` starts at `frontend/canvas.html` line 6209.
+   - It validates route crossings and calls `buildYamlForPage(activePage)` at
+     line 6215.
+   - `buildYamlForPage` starts at line 6141 and writes:
+     - `schema_version`, `kind`, `coordinate_system: gds_y_up`,
+       `canvas_size`, `project`, `name`, `type`, `version`.
+     - `pins` via `buildCanvasPinsYaml`.
+     - `instances` via `buildInstancesYaml`.
+     - `elements` via `buildElementsYaml`.
+     - `bundles` via `buildBundlesYaml`.
+
+3. Frontend sends the YAML to Flask:
+   - `fetch('/api/save-layout', ...)` at `frontend/canvas.html` line 6219.
+   - Body includes `project`, `cell`, and `content` at lines 6222-6226.
+
+4. Flask saves YAML and route sidecar:
+   - Route: `/api/save-layout` (`backend/server.py` line 713).
+   - Function: `save_layout` (`backend/server.py` line 715).
+   - `save_path = cell_file_path(project, cell)` (`backend/server.py` line 724).
+   - Writes the YAML content to disk (`backend/server.py` lines 727-728).
+   - Extracts route points into `<cell>.routes.yml` through
+     `write_route_points_sidecar` (`backend/server.py` line 729).
+
+5. Flask always uses the router-backed SVG preview:
+   - Preview output path is computed with `cell_svg_path`
+     (`backend/server.py` line 733).
+   - `create_routed_layout_svg(...)` is called unconditionally for preview
+     generation (`backend/server.py` lines 734-742).
+   - There is no production branch based on `bundles.*.links`; no-link and
+     linked layouts both use the same router path.
+
+6. Routed preview helper converts router GDS into SVG:
+   - `create_routed_layout_svg` starts at `backend/routed_layout_preview.py`
+     line 14.
+   - It loads the YAML string, gets the target cell name, and imports
+     `mxpic_router.build_project_gds` (`backend/routed_layout_preview.py` lines
+     25-32).
+   - It builds a temporary GDS with `target_cell_name=cell_name`
+     (`backend/routed_layout_preview.py` lines 37-46).
+   - It reads that temporary GDS with `gdstk.read_gds`
+     (`backend/routed_layout_preview.py` line 47).
+   - It writes the saved preview SVG with `top_cells[0].write_svg(output_path)`
+     (`backend/routed_layout_preview.py` line 51).
+
+Inside sibling router checkout:
+
+- `mxpic_router.build_project_gds` starts at
+  `../mxpic_router/mxpic_router/builder.py` line 12.
+- `_load_project_specs` reads all saved `.yml` / `.yaml` files from the project
+  directory (`../mxpic_router/mxpic_router/builder.py` line 46).
+- `load_cell_spec` reads YAML with `yaml.safe_load`
+  (`../mxpic_router/mxpic_router/eda_loader.py` line 80).
+- `parse_cell_dict` converts YAML into `CellSpec`, including `pins`,
+  `elements`, `instances`, and `bundles`
+  (`../mxpic_router/mxpic_router/eda_loader.py` lines 85-157).
+- `_build_cell` creates `with nd.Cell(name=spec.name) as top`
+  (`../mxpic_router/mxpic_router/builder.py` line 70).
+- `_build_cell` places basic, local, or PDK GDS instances and registers pins
+  (`../mxpic_router/mxpic_router/builder.py` lines 73-108).
+- `_route_link` draws routed geometry for each bundle link when links exist
+  (`../mxpic_router/mxpic_router/builder.py` line 269).
+- `nd.export_gds(topcells=[built_cells[top.name]], filename=output_path)`
+  writes the temporary routed GDS (`../mxpic_router/mxpic_router/builder.py`
+  line 37).
+
+## Build GDS: Click Button -> Saved YAML -> Router GDS
+
+Compact path:
+
+`Click Build GDS` -> Project Tree button calls `onBuildGds`
+(`frontend/canvas.html` line 2738) -> `handleBuildGds`
+(`frontend/canvas.html` line 6287) -> POST `/api/build-gds`
+(`frontend/canvas.html` line 6294) -> `build_gds`
+(`backend/server.py` line 775) -> `build_project_gds`
+(`backend/gds_builder.py` line 26) : read saved `.yml` files for project
+validation -> `_build_with_mxpic_router` (`backend/gds_builder.py` line 47) ->
+`mxpic_router` creates `nd.Cell` objects and exports `.gds` -> backend returns
+`download_url` -> frontend clicks a temporary download link.
+
+Detailed path:
+
+1. The `Build GDS` button is in the project tree header:
+   - `<button className="build-gds-btn" onClick={onBuildGds}>`
+     (`frontend/canvas.html` lines 2738-2739).
+   - `onBuildGds={handleBuildGds}` is passed into `LeftPanel`
+     (`frontend/canvas.html` line 6354).
+
+2. `handleBuildGds` calls the backend:
+   - Function starts at `frontend/canvas.html` line 6287.
+   - It validates route crossings for all non-preview pages
+     (`frontend/canvas.html` lines 6289-6290).
+   - It POSTs only `{ project: currentProjectName }` to `/api/build-gds`
+     (`frontend/canvas.html` lines 6294-6298).
+
+Important behavior:
+
+- `Build GDS` does not serialize the current in-memory canvas first.
+- It reads YAML files that already exist on disk.
+- Those YAML files are produced by `Build Layout` or by the separate `Save`
+  button, where `handleSaveProjectLayouts` saves every non-preview page with
+  `preview: false` (`frontend/canvas.html` lines 6253-6284).
+
+3. Flask creates a temporary export path and calls the GDS builder:
+   - Route: `/api/build-gds` (`backend/server.py` line 773).
+   - Function: `build_gds` (`backend/server.py` line 775).
+   - Old exports are cleaned (`backend/server.py` line 781).
+   - The project directory is resolved and validated
+     (`backend/server.py` lines 782-784).
+   - `create_export_path` creates `database/_exports/<uuid>/<project>.gds`
+     (`backend/server.py` line 785, `backend/pdk_access.py` lines 53-59).
+   - `build_project_gds(...)` is called (`backend/server.py` lines 786-792).
+
+4. `backend/gds_builder.py` delegates to `mxpic_router`:
+   - `build_project_gds` starts at `backend/gds_builder.py` line 26.
+   - `_load_project_cells(project_dir)` reads every saved `.yml` / `.yaml`
+     file for validation (`backend/gds_builder.py` line 73).
+   - `_build_with_mxpic_router` starts at `backend/gds_builder.py` line 47.
+   - `_build_with_mxpic_router` calls `ensure_router_path` and imports
+     `mxpic_router.build_project_gds` (`backend/gds_builder.py` lines 54-55).
+   - There is no production fallback to local gdstk or local Nazca builders.
+
+5. `mxpic_router` builds the final GDS:
+   - `mxpic_router.build_project_gds` starts at
+     `../mxpic_router/mxpic_router/builder.py` line 12.
+   - `_build_cell` creates one `nd.Cell` per `CellSpec`
+     (`../mxpic_router/mxpic_router/builder.py` line 70).
+   - `_resolve_pdk_asset` finds component YAML/GDS in the active PDK root
+     (`../mxpic_router/mxpic_router/builder.py` line 509).
+   - `_route_link` draws routed geometry when saved bundle links exist
+     (`../mxpic_router/mxpic_router/builder.py` line 269).
+   - `nd.export_gds(...)` writes the output GDS
+     (`../mxpic_router/mxpic_router/builder.py` line 37).
+
+## PDK Asset Resolution
+
+The active PDK root still comes from the EDA backend request/session state:
+
+- `current_pdk_root` uses `pdk_root_for_session`
+  (`backend/server.py` lines 196-198).
+- `pdk_root_for_session` chooses the root based on the logged-in user group
+  (`backend/pdk_access.py` lines 43-50).
+- Preview and GDS generation pass that PDK root into `mxpic_router`.
+- `mxpic_router._resolve_pdk_asset` resolves component YAML/GDS under that root
+  (`../mxpic_router/mxpic_router/builder.py` line 509).
+
+## Download Completion
+
+After GDS build:
+
+`build_gds` returns `download_url` (`backend/server.py` line 803) ->
+`handleBuildGds` creates a temporary `<a>` and clicks it
+(`frontend/canvas.html` lines 6309-6316) -> `/api/exports/<export_id>/<filename>`
+serves the GDS (`backend/server.py` lines 812-829) -> the temporary export
+folder is deleted when the response closes (`backend/server.py` line 829).
diff --git a/INTRANET_DEPLOYMENT.md b/INTRANET_DEPLOYMENT.md
index 8f85a18..5b5fb4a 100644
--- a/INTRANET_DEPLOYMENT.md
+++ b/INTRANET_DEPLOYMENT.md
@@ -6,6 +6,13 @@ Organization : OptiHK Limited
 -->
 # mxPIC EDA Intranet Deployment
 
+## Build-Time Router Stack
+
+The Flask server can launch for login, dashboard, canvas editing, YAML
+generation, and PDK browsing without importing `mxpic_router` or `mxpic_forge`.
+Build actions require the matched `mxpic_router` and `mxpic_forge` checkouts;
+SVG preview generation also requires `gdstk`.
+
 ## Start on the office LAN
 
 1. On the host computer, open PowerShell in this repository.
@@ -64,6 +71,13 @@ MXPIC_PORT=3000
 MXPIC_DEBUG=0
 MXPIC_SECRET_KEY=<long random string>
 MXPIC_COOKIE_SECURE=0
+MXPIC_PDK_PUBLIC_ROOT=<path-to-public-foundries>
+MXPIC_PDK_ATLAS_ROOT=<path-to-atlas-foundries>
 ```
 
 Set `MXPIC_COOKIE_SECURE=1` only when serving through HTTPS.
+
+PDK component metadata, GDS assets, and `technology.yml` manifests are all read
+from these role-scoped roots. If the variables are not set, the backend defaults
+to `../opt_pdk_public/foundries` for normal users/developers and
+`../opt_pdk_atlas/foundries` for managers.
diff --git a/PDK_TECHNOLOGY_XSECTION_LOADING.md b/PDK_TECHNOLOGY_XSECTION_LOADING.md
new file mode 100644
index 0000000..6aa54c9
--- /dev/null
+++ b/PDK_TECHNOLOGY_XSECTION_LOADING.md
@@ -0,0 +1,581 @@
+# PDK, Technology, and Xsection Loading Logic Path
+
+This document explains how the current code loads:
+
+- PDK component information: component folders, component YAML, images, and GDS assets.
+- Technology information: selected foundry/technology for each project.
+- Xsection information: routing cross-section defaults and Nazca layer bindings from `technology.yml`.
+
+Line numbers refer to the current codebase at the time this document was written.
+
+## Mental Model
+
+There are three related but separate data paths.
+
+1. Component PDK assets
+   - Source: role-controlled PDK trees:
+     - `opt_pdk_public/foundries`
+     - `opt_pdk_atlas/foundries`
+   - Controlled by user group through `pdk_root_for_session`
+     (`backend/pdk_access.py` line 43).
+   - Used for library browsing, component metadata, component images, and final
+     component GDS resolution.
+
+2. Technology registry and manifests
+   - Source: the same role-controlled PDK trees as component assets.
+   - Path: `<active_role_pdk_root>/<foundry>/<technology>/technology.yml`.
+   - Used to list available technologies, save the project technology choice,
+     load route defaults, and register Nazca layers/xsections.
+
+3. Saved project layout YAML
+   - Source: `database/<username>/layout/<project>/<cell>.yml`.
+   - Contains placed component paths and `bundles.*.links[*].xsection`.
+   - Consumed by `mxpic_router` when building SVG preview GDS or downloadable GDS.
+
+Important distinction:
+
+- The active role PDK root is now the single source of truth.
+- Normal/developer users read from `opt_pdk_public/foundries`.
+- Manager users read from `opt_pdk_atlas/foundries`.
+- The selected project technology scopes the library browser and selects which
+  `technology.yml` is loaded from that same role root.
+
+## Active Roots
+
+Backend startup defines the important paths:
+
+- `REPO_ROOT` (`backend/server.py` line 36) points two levels above
+  `backend/`.
+- There is no separate technology-manifest copy inside `mxpic_EDA`.
+
+Role-based PDK root:
+
+`Flask session user_group` -> `current_pdk_root`
+(`backend/server.py` line 196) -> `pdk_root_for_session`
+(`backend/pdk_access.py` line 43) -> `pdk_root_for_group`
+(`backend/pdk_access.py` line 27) : choose:
+
+- manager -> `MXPIC_PDK_ATLAS_ROOT` or `../opt_pdk_atlas/foundries`.
+- developers/user -> `MXPIC_PDK_PUBLIC_ROOT` or `../opt_pdk_public/foundries`.
+
+## Technology Selection Path
+
+Compact path:
+
+`Dashboard opens` -> `loadTechnologies` (`frontend/dashboard.html` line 1238)
+-> GET `/api/technologies` -> `list_technologies`
+(`backend/server.py` line 441) : scan `current_pdk_root()` ->
+return `{ foundry, technology, id, label }` -> dashboard fills the technology
+select.
+
+Detailed path:
+
+1. The dashboard calls `/api/technologies`:
+   - `loadTechnologies` starts at `frontend/dashboard.html` line 1238.
+   - It stores `data.technologies` and creates `<option>` values using
+     `tech.id`, for example `Silterra/EMO1_2ML_CU_Al_RDL`.
+
+2. The backend scans the technology registry:
+   - Route: `/api/technologies` (`backend/server.py` line 439).
+   - Function: `list_technologies` (`backend/server.py` line 441).
+   - It scans `current_pdk_root()`.
+   - A technology directory is exposed only when it contains `technology.yml`.
+   - For each valid directory pair it returns:
+     - `foundry`
+     - `technology`
+     - `id: foundry/technology`
+     - `label: foundry / technology`
+
+3. Creating a project stores the selected technology:
+   - Dashboard create click posts to `/api/projects`
+     (`frontend/dashboard.html` line 1303).
+   - Body contains `{ name, technology }`.
+   - Backend route: `/api/projects` (`backend/server.py` line 603).
+   - Function: `create_project` (`backend/server.py` line 605).
+   - It writes `.project.json` with:
+     - `name`
+     - `technology`
+   - Metadata helper path: `project_meta_path`
+     (`backend/server.py` line 228).
+   - Metadata writer: `write_project_meta`
+     (`backend/server.py` line 242).
+
+Saved metadata location:
+
+`database/<username>/layout/<project>/.project.json`
+
+Example:
+
+```json
+{
+  "name": "mxpic_project_1",
+  "technology": "Silterra/EMO1_2ML_CU_Al_RDL"
+}
+```
+
+## Technology Manifest Loading Path
+
+Compact path:
+
+`Canvas opens project` -> `loadProject` (`frontend/canvas.html` line 5030)
+-> GET `/api/projects/<project>` -> `get_project`
+(`backend/server.py` line 632) : returns saved `technology` -> frontend
+`loadTechnologyManifest` (`frontend/canvas.html` line 4056) -> GET
+`/api/technologies/<foundry>/<technology>/manifest` -> `read_technology_manifest`
+(`backend/technology_manifest.py` line 27) -> return full `technology.yml`
+manifest.
+
+Detailed path:
+
+1. Canvas loads project metadata:
+   - `loadProject` fetches `/api/projects/<project>`
+     (`frontend/canvas.html` line 5033).
+   - Backend `get_project` returns:
+     - project name
+     - saved cells
+     - `technology: read_project_meta(project_name).get("technology")`
+       (`backend/server.py` line 653).
+
+2. Canvas loads the selected technology manifest:
+   - `loadTechnologyManifest` starts at `frontend/canvas.html` line 4056.
+   - It expects technology IDs in `foundry/technology` format.
+   - It fetches:
+     `/api/technologies/<foundry>/<technology>/manifest`.
+   - If missing or invalid, it logs an error and uses
+     `FALLBACK_TECHNOLOGY_MANIFEST`.
+
+3. Backend validates and returns the manifest:
+   - Route:
+     `/api/technologies/<foundry>/<technology>/manifest`
+     (`backend/server.py` line 465).
+   - Function: `get_technology_manifest`
+     (`backend/server.py` line 467).
+   - It calls `read_technology_manifest`
+     (`backend/technology_manifest.py` line 27).
+   - The expected path is built by `technology_manifest_path`
+     (`backend/technology_manifest.py` line 16):
+
+```text
+<active_role_pdk_root>/<foundry>/<technology>/technology.yml
+```
+
+4. Backend manifest validation:
+   - `technology.yml` must exist.
+   - `manifest.xsections` must be a dictionary.
+   - `manifest.defaults` must be a dictionary.
+   - Otherwise the API returns 404 with a `TechnologyManifestError`.
+
+## Current `technology.yml` Structure
+
+Active example:
+
+`opt_pdk_public/foundries/Silterra/EMO1_2ML_CU_Al_RDL/technology.yml`
+
+For manager sessions, the equivalent file is read from
+`opt_pdk_atlas/foundries`.
+
+Important sections:
+
+- `schema_version` (`technology.yml` line 7).
+- `foundry` (`technology.yml` line 8).
+- `technology` (`technology.yml` line 9).
+- `layers` (`technology.yml` line 18).
+- `routing_types` (`technology.yml` line 41).
+- `defaults` (`technology.yml` line 44).
+- `xsections` (`technology.yml` line 50).
+
+Current xsections:
+
+- `strip` (`technology.yml` line 51).
+- `rib_low` (`technology.yml` line 58).
+- `metal_1` (`technology.yml` line 67).
+- `metal_2` (`technology.yml` line 74).
+
+Meaning of the main fields:
+
+- `layers`: maps technology layer names to GDS layer/datatype pairs.
+- `routing_types`: choices shown by the route editor.
+- `defaults`: default route `xsection`, `family`, `width`, `radius`, and
+  `routing_type`.
+- `xsections`: per-cross-section defaults and layer bindings.
+- `constants` and `source_class`: currently kept as manifest metadata. The
+  active frontend and router code do not consume them directly.
+
+## Frontend Xsection Usage
+
+Compact path:
+
+`technology.yml xsections` -> backend manifest API -> `technologyManifest`
+state (`frontend/canvas.html` line 3756) -> route editor dropdown and route
+defaults -> saved YAML `bundles.output_bus.links[*].xsection`.
+
+Detailed path:
+
+1. Fallback manifest:
+   - `FALLBACK_TECHNOLOGY_MANIFEST` is defined in
+     `frontend/canvas-helpers.js` line 105.
+   - It includes fallback `strip`, `rib_low`, `metal_1`, and `metal_2`
+     xsections.
+
+2. Canvas state:
+   - `projectTechnology` state is declared at `frontend/canvas.html` line 3755.
+   - `technologyManifest` state is declared at `frontend/canvas.html` line 3756.
+
+3. Route defaults:
+   - `getXsectionInfo` (`frontend/canvas-helpers.js` line 132) looks up
+     `manifest.xsections[xsection]`.
+   - `createRouteSettings` (`frontend/canvas-helpers.js` line 138) merges:
+     - manifest defaults
+     - selected xsection defaults
+     - user overrides saved on the edge
+   - Resulting route state always has:
+     - `xsection`
+     - `family`
+     - `width`
+     - `radius`
+     - `routing_type`
+
+4. Changing xsection in the route editor:
+   - Right panel builds available xsections from
+     `Object.keys(technologyManifest.xsections)`
+     (`frontend/canvas.html` line 2999).
+   - The xsection select calls `updateRouteXsection`
+     (`frontend/canvas.html` line 3037).
+   - `updateRouteXsection` refreshes family, default width, and default radius
+     (`frontend/canvas-helpers.js` line 167).
+
+5. Link toolbar choices:
+   - `linkXsectionChoices` is built from `technologyManifest.xsections`
+     (`frontend/canvas.html` line 3775).
+   - It prefers the order `strip`, `rib_low`, `metal_1`, `metal_2`, then any
+     extra xsections.
+
+## Component PDK Library Loading Path
+
+Compact path:
+
+`Canvas needs library` -> `fetchLibrary` (`frontend/canvas.html` line 4576)
+-> GET `/api/library?project=<project>` -> `pdk_root_for_request_project`
+(`backend/server.py` line 222) -> `scoped_pdk_root_for_project`
+(`backend/server.py` line 201) -> `findComps`
+(`backend/server.py` line 262) -> frontend library tree.
+
+Detailed path:
+
+1. Frontend requests the library:
+   - `fetchLibrary` calls `/api/library?project=<currentProjectName>`
+     (`frontend/canvas.html` line 4576).
+
+2. Backend chooses the PDK root for this request:
+   - Route: `/api/library` (`backend/server.py` line 854).
+   - Function: `getLib` uses `pdk_root_for_request_project`.
+   - `pdk_root_for_request_project` starts at `backend/server.py` line 222.
+   - If a project is supplied, it calls `scoped_pdk_root_for_project`.
+   - Otherwise it uses `current_pdk_root`.
+
+3. Project scoping:
+   - `scoped_pdk_root_for_project` starts at `backend/server.py` line 201.
+   - It reads the project `.project.json` technology field.
+   - It splits the value into `foundry/technology`.
+   - It scopes the role root to:
+
+```text
+<active_role_pdk_root>/<foundry>/<technology>
+```
+
+   - It only returns that scoped path if it exists and stays under the active
+     role root.
+   - If not valid, it falls back to the active role root.
+
+4. Component scanning:
+   - `findComps` starts at `backend/server.py` line 262.
+   - It walks the chosen PDK directory.
+   - Any folder containing a `.yml` file is treated as one component leaf.
+   - It stores component metadata:
+     - folder path
+     - first component YAML filename
+     - category
+     - relative component path
+   - `addCompsToTree` (`backend/server.py` line 290) converts this flat map
+     into the nested library tree returned to the canvas.
+
+Important detail:
+
+`getLib` scans the project-scoped directory but calls:
+
+```python
+findComps(comps_root, current_pdk_root())
+```
+
+This means the visible library is limited to the selected project technology,
+but each component `__path__` is stored relative to the base role PDK root, not
+relative to the scoped technology directory.
+
+For example, if the active role PDK root is:
+
+```text
+opt_pdk_public/foundries
+```
+
+and the project technology is:
+
+```text
+Silterra/EMO1_2ML_CU_Al_RDL
+```
+
+a component path saved into layout YAML can include:
+
+```text
+Silterra/EMO1_2ML_CU_Al_RDL/<category>/<component>/<component>
+```
+
+This is important because build and preview pass the base role PDK root into
+`mxpic_router`, and the saved component path can still resolve under that base
+root.
+
+## Component Metadata and Image Loading
+
+Component YAML path:
+
+`Canvas load/drop component` -> `loadComponentMetadata`
+(`frontend/canvas.html` line 4082) -> GET
+`/api/component/<component_name>?project=<project>` -> `readCompYaml`
+(`backend/server.py` line 345) -> return component YAML.
+
+Details:
+
+- Route: `/api/component/<component_name>` (`backend/server.py` line 869).
+- The backend uses the same project-scoped PDK root logic as `/api/library`.
+- `readCompYaml` walks the selected PDK root and matches the component folder
+  basename.
+- If the PDK root is under `opt_pdk_public` or `opt_pdk_atlas`, legacy
+  component metadata with `ports` is normalized to `pins`.
+
+Component image path:
+
+`Canvas thumbnail` -> `/api/component/<component_name>/image?project=<project>`
+-> `find_component_dir` (`backend/server.py` line 367) -> first
+`.png`, `.jpg`, `.jpeg`, or `.svg` in the component folder.
+
+Route:
+
+- `/api/component/<component_name>/image` (`backend/server.py` line 878).
+
+## Saved YAML: How PDK Paths and Xsections Are Written
+
+Compact path:
+
+`Build Layout` or `Save` -> `buildYamlForPage`
+(`frontend/canvas.html` line 6141) -> `findComponentPath`
+(`frontend/canvas.html` line 3659) -> `buildInstancesYaml`
+(`frontend/canvas-helpers.js` line 665) -> saved `instances.*.component`.
+
+Component path details:
+
+- `findComponentPath` searches the loaded library tree.
+- If a component node has `__path__`, that path is used.
+- `buildInstanceYaml` (`frontend/canvas-helpers.js` line 643) writes:
+
+```yaml
+instances:
+  <instance_name>:
+    component: <component path from library>
+```
+
+- Forge and basic components are special:
+  - Forge components save the forge component type.
+  - Basic components save names such as `waveguide`, `90 bend`, or `taper`.
+  - Normal PDK components save the PDK library path.
+
+Xsection path details:
+
+`Canvas edges` -> `buildBundlesYaml` (`frontend/canvas-helpers.js` line 988)
+-> `createRouteSettings` (`frontend/canvas-helpers.js` line 138) -> saved
+bundle links:
+
+```yaml
+bundles:
+  output_bus:
+    routing_type: euler_bend
+    links:
+      - from: <instance>:<pin>
+        to: <instance>:<pin>
+        xsection: strip
+        family: optical
+        width: 0.45
+        radius: 10
+        routing_type: euler_bend
+```
+
+The saved `xsection` field is the bridge from frontend route editing into
+`mxpic_router` and Nazca.
+
+## Build-Time Technology and PDK Loading
+
+Both SVG preview and final GDS now use the router-backed path.
+
+### SVG Preview
+
+Compact path:
+
+`POST /api/save-layout` -> `save_layout` (`backend/server.py` line 715)
+-> `create_routed_layout_svg` (`backend/routed_layout_preview.py` line 14)
+-> `mxpic_router.build_project_gds` -> temporary GDS -> `gdstk.write_svg`.
+
+Arguments passed from `save_layout`:
+
+- `pdk_root=current_pdk_root()` (`backend/server.py` line 737).
+- `technology_manifest_path=technology_manifest_path_for_project(project)`
+  (`backend/server.py` line 739).
+- `prefer_full_gds=prefer_full_gds_for_session(session)`
+  (`backend/server.py` line 740).
+
+The preview helper:
+
+- Imports `mxpic_router.build_project_gds`
+  (`backend/routed_layout_preview.py` line 32).
+- Builds a temporary GDS with the same PDK root and technology manifest path
+  (`backend/routed_layout_preview.py` lines 39-45).
+- Reads that GDS with `gdstk`.
+- Writes the SVG preview (`backend/routed_layout_preview.py` line 51).
+
+### Final GDS
+
+Compact path:
+
+`POST /api/build-gds` -> `build_gds` (`backend/server.py` line 775)
+-> `backend.gds_builder.build_project_gds` (`backend/gds_builder.py` line 26)
+-> `_build_with_mxpic_router` (`backend/gds_builder.py` line 47)
+-> `mxpic_router.build_project_gds`.
+
+Arguments passed from `build_gds`:
+
+- `current_pdk_root()` (`backend/server.py` line 789).
+- `technology_manifest_path=technology_manifest_path_for_project(project)`
+  (`backend/server.py` line 790).
+- `prefer_full_gds=prefer_full_gds_for_session(session)`
+  (`backend/server.py` line 791).
+
+`technology_manifest_path_for_project`:
+
+- Starts at `backend/server.py` line 183.
+- Reads the project technology from `.project.json`.
+- Builds:
+
+```text
+<active_role_pdk_root>/<foundry>/<technology>/technology.yml
+```
+
+- Returns the path only if it exists and stays under `current_pdk_root()`.
+
+## Inside `mxpic_router`
+
+Compact path:
+
+`mxpic_router.build_project_gds` (`../mxpic_router/mxpic_router/builder.py`
+line 12) -> `load_technology_manifest`
+(`../mxpic_router/mxpic_router/technology.py` line 6) ->
+`apply_technology_manifest` (`../mxpic_router/mxpic_router/technology.py`
+line 13) -> Nazca `nd.add_layer`, `nd.add_xsection`,
+`nd.add_layer2xsection`.
+
+Detailed path:
+
+1. Build starts:
+   - `build_project_gds` starts at
+     `../mxpic_router/mxpic_router/builder.py` line 12.
+   - It imports Nazca as `nd`.
+   - It loads the manifest from `technology_manifest_path`
+     (`../mxpic_router/mxpic_router/builder.py` line 23).
+   - It applies the manifest to Nazca
+     (`../mxpic_router/mxpic_router/builder.py` line 24).
+
+2. Technology manifest to Nazca:
+   - `load_technology_manifest` returns `{}` if the path is missing
+     (`../mxpic_router/mxpic_router/technology.py` line 6).
+   - `apply_technology_manifest` does nothing for an empty manifest.
+   - For each `manifest.layers` entry it calls:
+
+```python
+nd.add_layer(name=name, layer=(layer, datatype), overwrite=True)
+```
+
+   - For each `manifest.xsections` entry it calls:
+
+```python
+nd.add_xsection(name=xsection)
+nd.add_layer2xsection(...)
+```
+
+   - Supported layer binding keys are:
+     - `growx`
+     - `growy`
+     - `leftedge`
+     - `rightedge`
+
+3. Project YAML parsing:
+   - `_load_project_specs` reads saved `.yml` / `.yaml` files
+     (`../mxpic_router/mxpic_router/builder.py` line 46).
+   - `load_cell_spec` reads YAML
+     (`../mxpic_router/mxpic_router/eda_loader.py` line 80).
+   - `parse_cell_dict` converts dictionaries into `CellSpec`
+     (`../mxpic_router/mxpic_router/eda_loader.py` line 85).
+
+4. Link xsections:
+   - `LinkSpec.xsection` defaults to `strip`
+     (`../mxpic_router/mxpic_router/eda_loader.py` line 51).
+   - `BundleSpec.xsection` defaults to `strip`
+     (`../mxpic_router/mxpic_router/eda_loader.py` line 66).
+   - Bundle-level `xsection` is read at
+     `../mxpic_router/mxpic_router/eda_loader.py` line 137.
+   - Link-level `xsection` overrides bundle-level xsection at
+     `../mxpic_router/mxpic_router/eda_loader.py` line 142.
+   - If `family` is missing, `_family_from_xsection` maps metal-like xsections
+     to `electrical`, otherwise `optical`
+     (`../mxpic_router/mxpic_router/eda_loader.py` line 171).
+
+5. PDK asset resolution:
+   - `_resolve_pdk_asset` starts at
+     `../mxpic_router/mxpic_router/builder.py` line 509.
+   - It first tries the saved component path directly under `pdk_root`.
+   - If no direct directory exists, it scans the whole PDK root by component
+     folder basename.
+   - It reads the component YAML if present.
+   - It chooses GDS through `_find_gds`
+     (`../mxpic_router/mxpic_router/builder.py` line 533).
+   - Normal users prefer `<component>_BB.gds`; manager sessions can prefer
+     `<component>.gds`.
+
+6. Route generation:
+   - `_route_link` starts at
+     `../mxpic_router/mxpic_router/builder.py` line 269.
+   - It creates the route object with:
+
+```python
+Route(radius=link.radius or 10, width=link.width, xs=link.xsection, PCB=...)
+```
+
+   - Optical and electrical routes both use `link.xsection`; metal routes also
+     enable PCB-style routing for `metal_1` and `metal_2`.
+   - Nazca can generate geometry on the correct layers because
+     `apply_technology_manifest` already registered the xsection layer bindings.
+
+## Current Fallbacks and Observations
+
+- If a project has no saved technology, the frontend uses
+  `FALLBACK_TECHNOLOGY_MANIFEST`.
+- If `/api/technologies/<foundry>/<technology>/manifest` fails, the frontend
+  also uses `FALLBACK_TECHNOLOGY_MANIFEST`.
+- If build-time `technology_manifest_path_for_project` cannot find
+  `technology.yml`, `mxpic_router` receives no manifest path and Nazca
+  registration is skipped.
+- The library browser is project-scoped by selected technology, but preview and
+  GDS build pass the base role PDK root to `mxpic_router`.
+- This works because normal saved component paths include
+  `foundry/technology/...` relative to the base role PDK root.
+- Manually edited YAML with only a component folder name can still resolve, but
+  the router will scan the whole active PDK root and use the first matching
+  folder basename.
+- The legacy local GDS/SVG preview builder and local PDK GDS registry have been
+  removed from `mxpic_EDA`; active build and preview actions call the
+  router-backed API wrappers instead.
diff --git a/README.md b/README.md
index 5d8fef7..cae8cf4 100644
--- a/README.md
+++ b/README.md
@@ -7,4 +7,18 @@ Organization : OptiHK Limited
 # mxpic_EDA
 The EDA coding for the layout for optihk
 # requirements
-flask
\ No newline at end of file
+flask
+
+## Build-Time Router Stack
+
+Login, dashboard, canvas editing, YAML generation, and PDK browsing run without
+importing `mxpic_router` or `mxpic_forge`. Build actions require the matched
+`mxpic_router` and `mxpic_forge` checkouts; SVG preview generation also requires
+`gdstk`.
+
+## PDK and Technology Roots
+
+PDK component assets and `technology.yml` manifests are loaded from the same
+role-scoped PDK roots. Normal users and developers use
+`MXPIC_PDK_PUBLIC_ROOT` or `../opt_pdk_public/foundries`; managers use
+`MXPIC_PDK_ATLAS_ROOT` or `../opt_pdk_atlas/foundries`.
diff --git a/backend/PDK_libs/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.png b/backend/PDK_libs/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.png
deleted file mode 100644
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diff --git a/backend/PDK_libs/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml b/backend/PDK_libs/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml
deleted file mode 100644
index f9a7224..0000000
--- a/backend/PDK_libs/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml
+++ /dev/null
@@ -1,41 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: EC_SiN400_1310_1p0dB_L635_A0_QY_202604
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: New SiN edge couplers with high efficiency
-ports:
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-    y: 0.0
-    a: 180.0
-    width: 0.7
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-    width: None
-  a0:
-    x: 0.0
-    y: 0.0
-    a: 180.0
-    width: 0.0
-time: 20260505-170136
-box_size:
-- 646.0
-- 75.0
-file_size: 1.36 KB
diff --git a/backend/__pycache__/database.cpython-39.pyc b/backend/__pycache__/database.cpython-39.pyc
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diff --git a/backend/__pycache__/pdk_access.cpython-39.pyc b/backend/__pycache__/pdk_access.cpython-39.pyc
index be23ec1055e074d4fd9c385c00ee105b5f3db333..3be826e835d159b5a5ee14d86a50384c54c952ac 100644
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diff --git a/backend/__pycache__/routed_layout_preview.cpython-39.pyc b/backend/__pycache__/routed_layout_preview.cpython-39.pyc
index 832e6a24e84e2f1b6f1bc1347b31ee2bc35f95a2..90c5746acf37fa44264c7c7220945232e31b65b2 100644
GIT binary patch
delta 912
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diff --git a/backend/__pycache__/router_dependency.cpython-39.pyc b/backend/__pycache__/router_dependency.cpython-39.pyc
new file mode 100644
index 0000000000000000000000000000000000000000..5d1181b4a64808f0a9f0ef035a10355c9cb7e857
GIT binary patch
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diff --git a/backend/__pycache__/technology_manifest.cpython-39.pyc b/backend/__pycache__/technology_manifest.cpython-39.pyc
index 7f9f6388841172bc9a9b1e9f4cafe315b21964d0..8f6c75d0dd936785c3584402c1cdacbb33456dad 100644
GIT binary patch
delta 56
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delta 76
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diff --git a/backend/gds_builder.py b/backend/gds_builder.py
index f5e0249..b52c688 100644
--- a/backend/gds_builder.py
+++ b/backend/gds_builder.py
@@ -1,23 +1,22 @@
 # -----------------------------------------------------------------------------
-# Description: Backend integration wrapper for project GDS generation and build result handling.
-# Inside functions: build_project_gds, _build_with_mxpic_router, _load_project_cells, _ordered_cell_names, _cells_have_links, _cells_have_elements, _build_with_gdstk, _import_public_gds, _build_with_nazca, _build_nazca_element_cells, _build_nazca_element_cell, _element_port_offset, _safe_cell_name, _library_cell_by_name, _int, _number
+# Description: Backend integration wrapper for required mxpic_router project GDS generation.
+# Inside functions: build_project_gds, _build_with_mxpic_router, _load_project_cells
 # Developer : Qin Yue @ 2026
 # Organization : OptiHK Limited
 # -----------------------------------------------------------------------------
-import math
 import os
-import sys
 from dataclasses import dataclass, field
 from typing import Dict, List
 
 import yaml
 
-from pdk_registry import PdkRegistry
+from router_dependency import require_router_stack
 
 
 @dataclass
 class BuildResult:
     """Container for GDS build output paths, status details, and engine metadata."""
+
     output_path: str
     engine: str
     cells_built: List[str] = field(default_factory=list)
@@ -31,57 +30,18 @@ def build_project_gds(
     technology_manifest_path: str = None,
     prefer_full_gds: bool = False,
 ) -> BuildResult:
-    """Build a hierarchical project GDS from saved cell YAML files."""
+    """Build a hierarchical project GDS from saved cell YAML files with mxpic_router."""
     cells = _load_project_cells(project_dir)
     if not cells:
         raise ValueError("No saved cell YAML files found for this project")
 
-    # Prefer the routed builder whenever it is available because it understands
-    # bundle links, anchor connections, and PDK-aware routing rules.
-    try:
-        return _build_with_mxpic_router(
-            project_dir,
-            output_path,
-            pdk_public_root,
-            technology_manifest_path,
-            prefer_full_gds,
-        )
-    except ImportError as router_error:
-        if _cells_have_links(cells):
-            raise RuntimeError(
-                "Routed Build GDS requires mxpic_router, nazca, and mxpic_forge when layout links are present. "
-                f"Router import failed: {router_error}"
-            ) from router_error
-
-    # Placement-only projects can still be exported with local GDS engines when
-    # the routed builder is not installed.
-    registry = PdkRegistry(pdk_public_root, prefer_full_gds=prefer_full_gds)
-    os.makedirs(os.path.dirname(output_path), exist_ok=True)
-
-    # Port/Anchor elements are logical pin-bearing devices. Use Nazca for these
-    # layouts so each element can be a placed cell with local nd.Pin metadata.
-    if _cells_have_elements(cells):
-        try:
-            return _build_with_nazca(cells, output_path, registry)
-        except ImportError as nazca_error:
-            raise RuntimeError(
-                "Build GDS with Port/Anchor elements requires Nazca so element cells can preserve nd.Pin metadata. "
-                f"Nazca import failed: {nazca_error}"
-            ) from nazca_error
-
-    # gdstk is the preferred fallback for placement-only projects without
-    # Port/Anchor element pin metadata; Nazca remains a secondary fallback for
-    # environments where gdstk is not installed.
-    try:
-        return _build_with_gdstk(cells, output_path, registry)
-    except ImportError as gdstk_error:
-        try:
-            return _build_with_nazca(cells, output_path, registry)
-        except ImportError as nazca_error:
-            raise RuntimeError(
-                "Build GDS requires either gdstk or a working nazca installation. "
-                f"gdstk import failed: {gdstk_error}. nazca import failed: {nazca_error}"
-            ) from nazca_error
+    return _build_with_mxpic_router(
+        project_dir,
+        output_path,
+        pdk_public_root,
+        technology_manifest_path,
+        prefer_full_gds,
+    )
 
 
 def _build_with_mxpic_router(
@@ -91,12 +51,8 @@ def _build_with_mxpic_router(
     technology_manifest_path: str,
     prefer_full_gds: bool,
 ) -> BuildResult:
-    """Delegate routed project GDS generation to the external mxpic_router package."""
-    # mxpic_router lives beside this repository during local development, so add
-    # that sibling checkout to sys.path only when it exists.
-    router_root = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "mxpic_router"))
-    if os.path.isdir(router_root) and router_root not in sys.path:
-        sys.path.insert(0, router_root)
+    """Delegate project GDS generation to the required external mxpic_router package."""
+    require_router_stack()
     from mxpic_router import build_project_gds as build_routed_project_gds
 
     result = build_routed_project_gds(
@@ -126,228 +82,3 @@ def _load_project_cells(project_dir: str) -> Dict[str, dict]:
         cell_name = str(data.get("name") or os.path.splitext(filename)[0])
         cells[cell_name] = data
     return cells
-
-
-def _ordered_cell_names(cells: Dict[str, dict]) -> List[str]:
-    """Order cells so dependencies are built before cells that reference them."""
-    composites = [name for name, data in cells.items() if data.get("type") != "project"]
-    projects = [name for name, data in cells.items() if data.get("type") == "project"]
-    return composites + projects
-
-
-def _cells_have_links(cells: Dict[str, dict]) -> bool:
-    """Detect whether any saved cell contains bundle links that require routed building."""
-    for data in cells.values():
-        for bundle in (data.get("bundles") or {}).values():
-            if bundle.get("links"):
-                return True
-    return False
-
-
-def _cells_have_elements(cells: Dict[str, dict]) -> bool:
-    """Detect whether any saved cell contains Port/Anchor element objects."""
-    for data in cells.values():
-        elements = data.get("elements") or {}
-        for element in elements.values():
-            if str((element or {}).get("type") or "").lower() in {"port", "anchor"}:
-                return True
-    return False
-
-
-def _build_with_gdstk(cells: Dict[str, dict], output_path: str, registry: PdkRegistry) -> BuildResult:
-    """Assemble a project GDS with gdstk when Nazca or routed building is unavailable."""
-    import gdstk
-
-    library = gdstk.Library()
-    built_cells = {}
-    warnings = []
-
-    # Build composite cells before project cells so project-level references can
-    # reuse cells already inserted into the same GDS library.
-    for cell_name in _ordered_cell_names(cells):
-        data = cells[cell_name]
-        gds_cell = library.new_cell(_safe_cell_name(cell_name, built_cells))
-        built_cells[cell_name] = gds_cell
-        for instance_name, instance in (data.get("instances") or {}).items():
-            component = str(instance.get("component") or "")
-            x = _number(instance.get("x"))
-            y = _number(instance.get("y"))
-            rotation = math.radians(_number(instance.get("rotation")))
-            child = built_cells.get(component)
-            if child is None:
-                # External components are resolved through the active PDK
-                # registry and imported as references.
-                asset = registry.resolve(component)
-                if not asset.gds_path:
-                    warnings.append(f"Missing GDS for {instance_name}: {component}")
-                    continue
-                child = _import_public_gds(gdstk, library, asset.gds_path)
-            gds_cell.add(gdstk.Reference(child, origin=(x, y), rotation=rotation))
-
-    library.write_gds(output_path)
-    return BuildResult(
-        output_path=output_path,
-        engine="gdstk",
-        cells_built=list(built_cells.keys()),
-        warnings=warnings,
-    )
-
-
-def _import_public_gds(gdstk, library, gds_path: str):
-    """Import public PDK GDS geometry into the output library."""
-    source = gdstk.read_gds(gds_path)
-    top_cells = source.top_level()
-    if not top_cells:
-        raise ValueError(f"No top-level cell found in {gds_path}")
-    # Avoid adding duplicate cell names when multiple instances reference the
-    # same imported PDK component.
-    for source_cell in source.cells:
-        if _library_cell_by_name(library, source_cell.name) is None:
-            library.add(source_cell)
-    return top_cells[0]
-
-
-def _build_with_nazca(cells: Dict[str, dict], output_path: str, registry: PdkRegistry) -> BuildResult:
-    """Assemble a project GDS with Nazca cells and PDK component placements."""
-    import nazca as nd
-
-    warnings = []
-    built_cells = {}
-    ordered_names = _ordered_cell_names(cells)
-    # Nazca cells are built in dependency order and then the final project cell
-    # is exported as the top-level GDS.
-    for cell_name in ordered_names:
-        data = cells[cell_name]
-        element_cells = _build_nazca_element_cells(nd, cell_name, data.get("elements") or {}, built_cells)
-        with nd.Cell(cell_name) as current_cell:
-            for instance_name, instance in (data.get("instances") or {}).items():
-                component = str(instance.get("component") or "")
-                x = _number(instance.get("x"))
-                y = _number(instance.get("y"))
-                rotation = _number(instance.get("rotation"))
-                if component in built_cells:
-                    built_cells[component].put(x, y, rotation)
-                    continue
-                asset = registry.resolve(component)
-                if not asset.gds_path:
-                    warnings.append(f"Missing GDS for {instance_name}: {component}")
-                    continue
-                loaded = nd.load_gds(asset.gds_path)
-                loaded.put(x, y, rotation)
-            for element_name, element_cell in element_cells.items():
-                element = (data.get("elements") or {}).get(element_name) or {}
-                x = _number(element.get("x"))
-                y = _number(element.get("y"))
-                rotation = _number(element.get("angle"))
-                element_cell.put(x, y, rotation)
-        built_cells[cell_name] = current_cell
-
-    top_name = ordered_names[-1]
-    nd.export_gds(built_cells[top_name], filename=output_path)
-    return BuildResult(output_path=output_path, engine="nazca", cells_built=ordered_names, warnings=warnings)
-
-
-def _build_nazca_element_cells(nd, parent_cell_name: str, elements: dict, existing_cells: dict) -> Dict[str, object]:
-    """Build reusable Nazca cells for built-in Port and Anchor element objects."""
-    element_cells = {}
-    known_cells = dict(existing_cells or {})
-    for element_name, element in (elements or {}).items():
-        element_type = str((element or {}).get("type") or "").lower()
-        if element_type not in {"port", "anchor"}:
-            continue
-        raw_cell_name = f"{parent_cell_name}_{element_name}_{element_type}"
-        cell_name = _safe_cell_name(raw_cell_name, {**known_cells, **element_cells})
-        element_cell = _build_nazca_element_cell(nd, cell_name, {**(element or {}), "name": str(element_name)})
-        element_cells[str(element_name)] = element_cell
-    return element_cells
-
-
-def _build_nazca_element_cell(nd, cell_name: str, element: dict):
-    """Create one local Port or Anchor cell whose pins are placed in local coordinates."""
-    element = element or {}
-    element_type = str(element.get("type") or "").lower()
-    width = _number(element.get("width"), 0.5)
-    port_number = max(1, _int(element.get("pin_number", element.get("pinNumber", element.get("port_number", element.get("portNumber")))), 1))
-    pitch = _number(element.get("pitch"), 10.0)
-    with nd.Cell(name=cell_name) as element_cell:
-        if element_type == "port":
-            for index, pin_name in enumerate(_element_pin_names(cell_name, element, port_number, "port")):
-                y = 0.0 if port_number == 1 else _element_port_offset(index, port_number, pitch)
-                nd.Pin(pin_name, width=width).put(0.0, y, 180.0)
-            return element_cell
-
-        anchor_pin_names = _element_pin_names(cell_name, element, port_number, "anchor")
-        for index in range(port_number):
-            y = -15.0 + _element_port_offset(index, port_number, pitch)
-            nd.Pin(anchor_pin_names[index * 2], width=width).put(0.0, y, 180.0)
-            nd.Pin(anchor_pin_names[index * 2 + 1], width=width).put(0.0, y, 0.0)
-    return element_cell
-
-
-def _element_port_offset(index: int, count: int, pitch: float) -> float:
-    """Return the local y offset for one repeated Port/Anchor pin."""
-    return ((max(1, count) - 1) / 2 - index) * pitch
-
-
-def _element_pin_names(cell_name: str, element: dict, count: int, element_type: str) -> List[str]:
-    """Return local element pin names, using YAML overrides when present."""
-    raw_pins = [pin for pin in (element.get("pins") or []) if isinstance(pin, dict)]
-    default_base = _safe_pin_name(str(element.get("name") or cell_name).replace("_port", "").replace("_anchor", ""))
-    roles = []
-    if element_type == "port":
-        roles = [f"io{index + 1}" for index in range(count)]
-    else:
-        for index in range(count):
-            roles.extend([f"a{index + 1}", f"b{index + 1}"])
-    by_role = {str(pin.get("role") or ""): str(pin.get("name") or "") for pin in raw_pins}
-    by_index = [str(pin.get("name") or "") for pin in raw_pins]
-    names = []
-    for index, role in enumerate(roles):
-        name = by_role.get(role) or (by_index[index] if index < len(by_index) else "") or f"{default_base}_{role}"
-        names.append(_safe_pin_name(name))
-    return names
-
-
-def _safe_pin_name(name: str) -> str:
-    """Generate a backend-safe pin name for local Nazca element pins."""
-    return "".join(ch if ch.isalnum() or ch == "_" else "_" for ch in str(name or "pin"))
-
-
-def _safe_cell_name(name: str, existing: dict) -> str:
-    """Generate a backend-safe unique cell name for GDS/Nazca libraries."""
-    base = "".join(ch if ch.isalnum() or ch in "._$" else "_" for ch in str(name)) or "cell"
-    candidate = base
-    counter = 1
-    used = {cell.name for cell in existing.values()}
-    while candidate in used:
-        counter += 1
-        candidate = f"{base}_{counter}"
-    return candidate
-
-
-def _library_cell_by_name(library, name: str):
-    """Find a cell object in a loaded layout library by name."""
-    for cell in library.cells:
-        if cell.name == name:
-            return cell
-    return None
-
-
-def _int(value, default=0) -> int:
-    """Convert integer YAML values with a stable default."""
-    try:
-        if value is None or value == "":
-            return default
-        return int(float(value))
-    except (TypeError, ValueError):
-        return default
-
-
-def _number(value, default=0.0) -> float:
-    """Convert numeric YAML values to floats with a stable default."""
-    try:
-        if value is None or value == "":
-            return default
-        return float(value)
-    except (TypeError, ValueError):
-        return default
diff --git a/backend/layout_preview.py b/backend/layout_preview.py
deleted file mode 100644
index a3ecbde..0000000
--- a/backend/layout_preview.py
+++ /dev/null
@@ -1,154 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: Layout preview helpers for generating SVG previews from saved layout YAML.
-# Inside functions: create_layout_svg_from_gds, _create_with_gdstk, _build_gdstk_cell, _resolve_child_cell, _import_gds_cell, _create_with_nazca, _load_local_layout, _safe_cell_name, _library_cell_by_name, _number
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-import os
-from typing import Dict, Optional
-
-import yaml
-
-def create_layout_svg_from_gds(yaml_content: str, output_path: str, pdk_registry, project_dir: str = None) -> str:
-    """Create an SVG preview by placing real public _BB.gds cells from layout YAML."""
-    layout = yaml.safe_load(yaml_content) or {}
-    # Try gdstk first because it can write SVG directly; keep Nazca as a GDS
-    # placement fallback for environments where gdstk is unavailable.
-    try:
-        return _create_with_gdstk(layout, output_path, pdk_registry, project_dir)
-    except ImportError as gdstk_error:
-        try:
-            return _create_with_nazca(layout, output_path, pdk_registry, project_dir)
-        except ImportError as nazca_error:
-            raise RuntimeError(
-                "Layout SVG requires GDS geometry support. Install gdstk, or fix nazca dependencies. "
-                f"gdstk import failed: {gdstk_error}. nazca import failed: {nazca_error}"
-            ) from nazca_error
-
-
-def _create_with_gdstk(layout: dict, output_path: str, pdk_registry, project_dir: Optional[str]) -> str:
-    """Generate preview SVG geometry using gdstk import and placement APIs."""
-    import gdstk
-
-    library = gdstk.Library()
-    cell_cache = {}
-    top = _build_gdstk_cell(gdstk, library, layout, pdk_registry, project_dir, cell_cache)
-    os.makedirs(os.path.dirname(output_path), exist_ok=True)
-    top.write_svg(output_path)
-    return output_path
-
-
-def _build_gdstk_cell(gdstk, library, layout: dict, pdk_registry, project_dir: Optional[str], cell_cache: Dict):
-    """Build or reuse a gdstk cell for a saved layout document."""
-    cell_name = _safe_cell_name(layout.get("name") or "layout", library)
-    top = library.new_cell(cell_name)
-
-    # Each saved instance becomes a GDS reference to either another project cell
-    # or a resolved PDK asset.
-    for instance_name, instance in (layout.get("instances") or {}).items():
-        component = str(instance.get("component") or "")
-        x = _number(instance.get("x"))
-        y = _number(instance.get("y"))
-        rotation = _number(instance.get("rotation")) * 3.141592653589793 / 180
-        child = _resolve_child_cell(gdstk, library, component, pdk_registry, project_dir, cell_cache)
-        if child is None:
-            raise FileNotFoundError(f"Unable to resolve _BB.gds for instance {instance_name}: {component}")
-        top.add(gdstk.Reference(child, origin=(x, y), rotation=rotation))
-
-    return top
-
-
-def _resolve_child_cell(gdstk, library, component: str, pdk_registry, project_dir: Optional[str], cell_cache: Dict):
-    """Resolve a placed child component from local cells or PDK assets."""
-    if component in cell_cache:
-        return cell_cache[component]
-
-    # Project-local composite cells are resolved before external PDK components
-    # so nested user-created cells can appear in preview output.
-    local_layout = _load_local_layout(component, project_dir)
-    if local_layout is not None:
-        child = _build_gdstk_cell(gdstk, library, local_layout, pdk_registry, project_dir, cell_cache)
-        cell_cache[component] = child
-        return child
-
-    asset = pdk_registry.resolve(component)
-    if not asset.gds_path:
-        return None
-    child = _import_gds_cell(gdstk, library, asset.gds_path)
-    cell_cache[component] = child
-    return child
-
-
-def _import_gds_cell(gdstk, library, gds_path: str):
-    """Import a GDS file and return the first usable cell for placement."""
-    source = gdstk.read_gds(gds_path)
-    top_cells = source.top_level()
-    if not top_cells:
-        raise ValueError(f"No top-level cell found in {gds_path}")
-    # Reuse already-imported cells by name to keep the preview library compact.
-    for source_cell in source.cells:
-        if _library_cell_by_name(library, source_cell.name) is None:
-            library.add(source_cell)
-    return top_cells[0]
-
-
-def _create_with_nazca(layout: dict, output_path: str, pdk_registry, project_dir: Optional[str]) -> str:
-    """Generate preview SVG geometry using Nazca when gdstk is unavailable."""
-    import nazca as nd
-
-    png_path = os.path.splitext(output_path)[0] + ".gds"
-    # Nazca can place the same GDS references as the preview path, but this
-    # backend still requires gdstk for final SVG conversion.
-    with nd.Cell(str(layout.get("name") or "layout")) as top:
-        for instance_name, instance in (layout.get("instances") or {}).items():
-            component = str(instance.get("component") or "")
-            asset = pdk_registry.resolve(component)
-            if not asset.gds_path:
-                raise FileNotFoundError(f"Unable to resolve _BB.gds for instance {instance_name}: {component}")
-            loaded = nd.load_gds(asset.gds_path)
-            loaded.put(_number(instance.get("x")), _number(instance.get("y")), _number(instance.get("rotation")))
-    nd.export_gds(top, filename=png_path)
-    raise RuntimeError(
-        "Nazca can build the placed GDS, but SVG preview export requires gdstk in this backend."
-    )
-
-
-def _load_local_layout(component: str, project_dir: Optional[str]) -> Optional[dict]:
-    """Load a project-local composite layout referenced by another cell."""
-    if not project_dir or "/" in component or "\\" in component or component == "generate_with_forge":
-        return None
-    for ext in (".yml", ".yaml"):
-        path = os.path.join(project_dir, f"{component}{ext}")
-        if os.path.exists(path):
-            with open(path, "r", encoding="utf-8") as file:
-                return yaml.safe_load(file) or {}
-    return None
-
-
-def _safe_cell_name(name, library) -> str:
-    """Generate a backend-safe unique cell name for GDS/Nazca libraries."""
-    base = "".join(ch if ch.isalnum() or ch in "._$" else "_" for ch in str(name)) or "layout"
-    candidate = base
-    counter = 1
-    while _library_cell_by_name(library, candidate) is not None:
-        counter += 1
-        candidate = f"{base}_{counter}"
-    return candidate
-
-
-def _library_cell_by_name(library, name: str):
-    """Find a cell object in a loaded layout library by name."""
-    for cell in library.cells:
-        if cell.name == name:
-            return cell
-    return None
-
-
-def _number(value, default=0.0) -> float:
-    """Convert numeric YAML values to floats with a stable default."""
-    try:
-        if value is None or value == "":
-            return default
-        return float(value)
-    except (TypeError, ValueError):
-        return default
diff --git a/backend/pdk_registry.py b/backend/pdk_registry.py
deleted file mode 100644
index ccd9386..0000000
--- a/backend/pdk_registry.py
+++ /dev/null
@@ -1,132 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK registry scanning helpers for finding component YAML/GDS assets and building library trees.
-# Inside functions: __init__, resolve, _find_yaml, _find_gds, _load_yaml, _inside_root
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-import os
-from dataclasses import dataclass
-from typing import Optional
-
-import yaml
-
-
-@dataclass
-class PdkAsset:
-    """Container describing the YAML and GDS assets resolved for a PDK component."""
-    component: str
-    yaml_path: Optional[str] = None
-    gds_path: Optional[str] = None
-    metadata: Optional[dict] = None
-
-
-class PdkRegistry:
-    """Resolve public PDK component names to metadata and public GDS assets."""
-
-    def __init__(self, public_root: str, prefer_full_gds: bool = False):
-        """Store the active PDK root and cache resolved component assets."""
-        self.public_root = os.path.abspath(public_root)
-        self.prefer_full_gds = prefer_full_gds
-        self._asset_cache = {}
-
-    def resolve(self, component: str) -> PdkAsset:
-        """Resolve YAML and GDS assets for a requested component key."""
-        key = (component or "").strip().replace("\\", "/").strip("/")
-        if not key:
-            return PdkAsset(component=component)
-        if key in self._asset_cache:
-            return self._asset_cache[key]
-
-        yaml_path = self._find_yaml(key)
-        gds_path = self._find_gds(key, yaml_path)
-        metadata = self._load_yaml(yaml_path) if yaml_path else None
-        asset = PdkAsset(component=component, yaml_path=yaml_path, gds_path=gds_path, metadata=metadata)
-        self._asset_cache[key] = asset
-        return asset
-
-    def _find_yaml(self, key: str) -> Optional[str]:
-        """Locate the component YAML description file in the active PDK tree."""
-        # Try direct component paths first so saved YAML component references
-        # resolve without scanning the whole PDK tree.
-        direct = os.path.join(self.public_root, *key.split("/"))
-        candidates = []
-        if direct.lower().endswith((".yml", ".yaml")):
-            candidates.append(direct)
-        else:
-            name = key.split("/")[-1]
-            candidates.append(os.path.join(direct, f"{name}.yml"))
-            candidates.append(os.path.join(direct, f"{name}.yaml"))
-
-        for candidate in candidates:
-            if self._inside_root(candidate) and os.path.exists(candidate):
-                return os.path.abspath(candidate)
-
-        name = key.split("/")[-1]
-        # Fall back to a tree scan for older saved references that only stored
-        # the component folder name.
-        for root, dirs, files in os.walk(self.public_root):
-            if os.path.basename(root) == name:
-                for filename in files:
-                    if filename.lower().endswith((".yml", ".yaml")):
-                        return os.path.join(root, filename)
-                dirs.clear()
-        return None
-
-    def _find_gds(self, key: str, yaml_path: Optional[str]) -> Optional[str]:
-        """Locate the best matching GDS asset for a component YAML or key."""
-        search_dir = os.path.dirname(yaml_path) if yaml_path else os.path.join(self.public_root, *key.split("/"))
-        name = key.split("/")[-1]
-        # Normal users prefer black-box GDS for fast previews; manager sessions
-        # can prefer full layout geometry for complete export.
-        if self.prefer_full_gds:
-            candidates = [
-                os.path.join(search_dir, f"{name}.gds"),
-                os.path.join(search_dir, f"{name}_BB.gds"),
-            ]
-        else:
-            candidates = [
-                os.path.join(search_dir, f"{name}_BB.gds"),
-                os.path.join(search_dir, f"{name}.gds"),
-            ]
-        for candidate in candidates:
-            if self._inside_root(candidate) and os.path.exists(candidate):
-                return os.path.abspath(candidate)
-        # If the expected filename is missing, choose the first available GDS in
-        # the component folder while respecting the full-vs-BB preference.
-        if os.path.isdir(search_dir):
-            gds_files = sorted(filename for filename in os.listdir(search_dir) if filename.lower().endswith(".gds"))
-            full_files = [filename for filename in gds_files if not filename.lower().endswith("_bb.gds")]
-            bb_files = [filename for filename in gds_files if filename.lower().endswith("_bb.gds")]
-            ordered = (full_files + bb_files) if self.prefer_full_gds else (bb_files + full_files)
-            if ordered:
-                return os.path.join(search_dir, ordered[0])
-        return None
-
-    def _load_yaml(self, yaml_path: Optional[str]) -> Optional[dict]:
-        """Read a YAML component metadata file into a dictionary."""
-        if not yaml_path:
-            return None
-        with open(yaml_path, "r", encoding="utf-8") as file:
-            data = yaml.safe_load(file) or {}
-        return self._normalize_pdk_pins(data)
-
-    def _normalize_pdk_pins(self, data: dict) -> dict:
-        """Treat legacy PDK `ports` metadata as `pins` inside approved PDK roots."""
-        if (
-            self._allows_legacy_ports_as_pins()
-            and isinstance(data, dict)
-            and "pins" not in data
-            and isinstance(data.get("ports"), dict)
-        ):
-            data = dict(data)
-            data["pins"] = data["ports"]
-        return data
-
-    def _allows_legacy_ports_as_pins(self) -> bool:
-        normalized = self.public_root.replace("\\", "/").lower()
-        return "/opt_pdk_public/" in f"{normalized}/" or "/opt_pdk_atlas/" in f"{normalized}/"
-
-    def _inside_root(self, path: str) -> bool:
-        """Check that a candidate asset path remains inside the permitted PDK root."""
-        target = os.path.abspath(path)
-        return target == self.public_root or target.startswith(self.public_root + os.sep)
diff --git a/backend/routed_layout_preview.py b/backend/routed_layout_preview.py
index 2ee1a44..305ffc5 100644
--- a/backend/routed_layout_preview.py
+++ b/backend/routed_layout_preview.py
@@ -5,11 +5,12 @@
 # Organization : OptiHK Limited
 # -----------------------------------------------------------------------------
 import os
-import sys
 import tempfile
 
 import yaml
 
+from router_dependency import require_router_stack
+
 
 def create_routed_layout_svg(
     yaml_content: str,
@@ -20,15 +21,11 @@ def create_routed_layout_svg(
     prefer_full_gds: bool = False,
 ) -> str:
     """Create an SVG preview from routed GDS geometry generated by mxpic_router."""
+    require_router_stack(require_gdstk=True)
     import gdstk
 
     layout = yaml.safe_load(yaml_content) or {}
     cell_name = str(layout.get("name") or "layout")
-    # mxpic_router is kept as a sibling repository, so the backend adds it to
-    # sys.path only when the local checkout is available.
-    router_root = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "mxpic_router"))
-    if os.path.isdir(router_root) and router_root not in sys.path:
-        sys.path.insert(0, router_root)
     from mxpic_router import build_project_gds
 
     os.makedirs(os.path.dirname(output_path), exist_ok=True)
diff --git a/backend/router_dependency.py b/backend/router_dependency.py
new file mode 100644
index 0000000..e7e286f
--- /dev/null
+++ b/backend/router_dependency.py
@@ -0,0 +1,77 @@
+# -----------------------------------------------------------------------------
+# Description: Build-time mxpic_router runtime dependency validation helpers.
+# Inside functions: ensure_router_path, require_router_stack
+# Developer : Qin Yue @ 2026
+# Organization : OptiHK Limited
+# -----------------------------------------------------------------------------
+import importlib
+import os
+import sys
+from dataclasses import dataclass, field
+from typing import List
+
+
+@dataclass
+class RouterStackStatus:
+    """Summary of the router stack checks completed for a build action."""
+
+    ok: bool
+    router_root: str
+    checked: List[str] = field(default_factory=list)
+
+
+class RouterStackUnavailable(RuntimeError):
+    """Raised when a build action needs the external router stack but it is absent."""
+    pass
+
+
+def ensure_router_path() -> str:
+    """Add the sibling mxpic_router checkout to import resolution when present."""
+    router_root = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "mxpic_router"))
+    if os.path.isdir(router_root) and router_root not in sys.path:
+        sys.path.insert(0, router_root)
+    return router_root
+
+
+def require_router_stack(require_gdstk: bool = False) -> RouterStackStatus:
+    """Validate the runtime stack required for build-time router actions."""
+    router_root = ensure_router_path()
+    checked = []
+    missing = []
+
+    try:
+        importlib.import_module("mxpic_router")
+        checked.append("mxpic_router")
+    except Exception as exc:
+        missing.append(f"mxpic_router: {exc}")
+
+    try:
+        importlib.import_module("nazca")
+        checked.append("nazca")
+    except Exception as exc:
+        missing.append(f"nazca: {exc}")
+
+    if require_gdstk:
+        try:
+            importlib.import_module("gdstk")
+            checked.append("gdstk")
+        except Exception as exc:
+            missing.append(f"gdstk: {exc}")
+
+    try:
+        router_builder = importlib.import_module("mxpic_router.builder")
+        route_factory = getattr(router_builder, "_import_mxpic_forge_route")
+        route_factory()
+        checked.append("mxpic_forge Route")
+    except Exception as exc:
+        missing.append(f"mxpic_forge Route: {exc}")
+
+    if missing:
+        details = "; ".join(missing)
+        raise RouterStackUnavailable(
+            "Required mxpic_router runtime stack is unavailable. "
+            "Build actions require the matched mxpic_router and mxpic_forge checkouts, "
+            f"Nazca, and gdstk for SVG preview generation. Details: {details}"
+        )
+
+    return RouterStackStatus(ok=True, router_root=router_root, checked=checked)
diff --git a/backend/server.py b/backend/server.py
index 8a0dcbd..1d422d7 100644
--- a/backend/server.py
+++ b/backend/server.py
@@ -1,6 +1,6 @@
 # -----------------------------------------------------------------------------
 # Description: Flask backend API server for authentication, project management, PDK library access, layout preview, and GDS build endpoints.
-# Inside functions: no_cache_response, login_required_json, wrapper, request_ip, record_action, safe_name, user_layout_root, project_root, cell_file_path, cell_svg_path, cell_routes_path, write_route_points_sidecar, project_gds_path, technology_manifest_path_for_project, current_pdk_root, current_pdk_registry, scoped_pdk_root_for_project, pdk_root_for_request_project, project_meta_path, read_project_meta
+# Inside functions: no_cache_response, login_required_json, wrapper, request_ip, record_action, safe_name, user_layout_root, project_root, cell_file_path, cell_svg_path, cell_routes_path, write_route_points_sidecar, project_gds_path, technology_manifest_path_for_project, current_pdk_root, scoped_pdk_root_for_project, pdk_root_for_request_project, project_meta_path, read_project_meta
 # Developer : Qin Yue @ 2026
 # Organization : OptiHK Limited
 # -----------------------------------------------------------------------------
@@ -17,15 +17,14 @@ from werkzeug.security import check_password_hash
 import database  
 from flask import Response
 from gds_builder import build_project_gds
-from layout_preview import create_layout_svg_from_gds
-from pdk_registry import PdkRegistry
 from pdk_access import (
     cleanup_expired_exports,
     create_export_path,
     pdk_root_for_session,
     prefer_full_gds_for_session,
 )
-from routed_layout_preview import create_routed_layout_svg, layout_has_links
+from router_dependency import RouterStackUnavailable
+from routed_layout_preview import create_routed_layout_svg
 from technology_manifest import TechnologyManifestError, read_technology_manifest
 
 # --- Path Configurations ---
@@ -35,12 +34,6 @@ BASE_DIR = os.path.dirname(os.path.abspath(__file__))
 FRONTEND_DIR = os.path.join(BASE_DIR, '..', 'frontend')
 
 REPO_ROOT = os.path.abspath(os.path.join(BASE_DIR, '..', '..'))
-PDK_PUBLIC_ROOT = os.path.abspath(os.environ.get(
-    'MXPIC_PDK_PUBLIC_ROOT',
-    os.path.join(REPO_ROOT, 'opt_pdk_public', 'foundries')
-))
-EDA_PDK_ROOT = os.path.abspath(os.path.join(BASE_DIR, '..', 'mxpic', 'PDKs'))
-YML_PATH = os.path.join(BASE_DIR, '..', 'mxpic', 'PDKs', 'Silterra', 'directories.yaml')
 # Component/category icons are served from backend/icons for the library panel.
 ICONS_DIR = os.path.join(BASE_DIR, 'icons') 
 
@@ -181,27 +174,32 @@ def project_gds_path(project_name):
     return os.path.join(project_root(project_name), f"{safe_name(project_name, 'project_1')}.gds")
 
 
-def technology_manifest_path_for_project(project_name):
-    """Return the stored technology manifest path for a project."""
-    technology_id = read_project_meta(project_name).get("technology") or ""
-    if "/" not in technology_id:
-        return None
-    foundry, technology = technology_id.split("/", 1)
-    path = os.path.abspath(os.path.join(EDA_PDK_ROOT, safe_name(foundry, ''), safe_name(technology, ''), "technology.yml"))
-    # Keep stored project metadata from escaping the local EDA PDK root.
-    if path.startswith(EDA_PDK_ROOT + os.sep) and os.path.exists(path):
-        return path
-    return None
-
-
 def current_pdk_root():
     """Resolve the active PDK root for the current request session."""
     return pdk_root_for_session(session, REPO_ROOT)
 
 
-def current_pdk_registry():
-    """Create a PDK registry configured for the current session scope."""
-    return PdkRegistry(current_pdk_root(), prefer_full_gds=prefer_full_gds_for_session(session))
+def technology_manifest_path_for_pdk_root(pdk_root, foundry, technology):
+    """Return a safe technology.yml path under a role-scoped PDK root."""
+    base_root = os.path.abspath(pdk_root)
+    path = os.path.abspath(os.path.join(
+        base_root,
+        safe_name(foundry, ''),
+        safe_name(technology, ''),
+        "technology.yml"
+    ))
+    if path.startswith(base_root + os.sep) and os.path.exists(path):
+        return path
+    return None
+
+
+def technology_manifest_path_for_project(project_name):
+    """Return the stored technology manifest path for a project and session."""
+    technology_id = read_project_meta(project_name).get("technology") or ""
+    if "/" not in technology_id:
+        return None
+    foundry, technology = technology_id.split("/", 1)
+    return technology_manifest_path_for_pdk_root(current_pdk_root(), foundry, technology)
 
 
 def scoped_pdk_root_for_project(project_name):
@@ -265,6 +263,14 @@ def ensure_project_path(project_name):
 # These helpers turn the active PDK folder structure into the nested component
 # library tree shown in the canvas sidebar.
 
+def component_yml_files(files):
+    """Return component metadata YAML files, excluding technology manifests."""
+    return [
+        f for f in files
+        if f.lower().endswith(('.yml', '.yaml')) and f.lower() != "technology.yml"
+    ]
+
+
 def findComps(baseDir, path_root=None):
     """Scan component folders, return map of paths -> component info."""
     compMap = {}
@@ -273,7 +279,7 @@ def findComps(baseDir, path_root=None):
     # A folder containing a YAML file is treated as a component leaf; scanning
     # stops below that leaf so nested assets do not pollute the library tree.
     for root, dirs, files in os.walk(baseDir):
-        ymlFiles = [f for f in files if f.endswith('.yml')]
+        ymlFiles = component_yml_files(files)
         if ymlFiles:
             parentDir = os.path.dirname(root)
             relPath = os.path.relpath(parentDir, refDir)
@@ -356,7 +362,7 @@ def readCompYaml(compName, comps_root=None):
     for root, dirs, files in os.walk(search_root):
         if os.path.basename(root) == compName:
             dirs.clear()
-            ymlFiles = [f for f in files if f.endswith('.yml')]
+            ymlFiles = component_yml_files(files)
             if ymlFiles:
                 ymlPath = os.path.join(root, ymlFiles[0])
                 with open(ymlPath, 'r', encoding='utf-8') as f:
@@ -445,11 +451,11 @@ def health_check():
 @app.route('/api/technologies', methods=['GET'])
 @login_required_json
 def list_technologies():
-    """List technology choices from mxpic/PDKs/<foundry>/<technology>."""
+    """List technology choices from the active role-scoped PDK root."""
     technologies = []
-    pdks_root = EDA_PDK_ROOT
-    # Technology choices are built from directory names because each technology
-    # folder owns its generated technology.yml manifest.
+    pdks_root = current_pdk_root()
+    # Technology choices are built from foundry/technology directories under the
+    # role PDK root, and only folders with technology.yml are exposed.
     if os.path.isdir(pdks_root):
         for foundry in sorted(os.listdir(pdks_root)):
             foundry_path = os.path.join(pdks_root, foundry)
@@ -459,6 +465,8 @@ def list_technologies():
                 technology_path = os.path.join(foundry_path, technology)
                 if not os.path.isdir(technology_path):
                     continue
+                if not os.path.exists(os.path.join(technology_path, "technology.yml")):
+                    continue
                 technologies.append({
                     "foundry": foundry,
                     "technology": technology,
@@ -473,11 +481,7 @@ def list_technologies():
 def get_technology_manifest(foundry, technology):
     """Return the routing and layer manifest for a selected technology."""
     try:
-        manifest = read_technology_manifest(
-            EDA_PDK_ROOT,
-            safe_name(foundry, ''),
-            safe_name(technology, '')
-        )
+        manifest = read_technology_manifest(current_pdk_root(), safe_name(foundry, ''), safe_name(technology, ''))
         return jsonify({"manifest": manifest})
     except TechnologyManifestError as e:
         return jsonify({"error": str(e)}), 404
@@ -735,11 +739,11 @@ def save_layout():
         write_route_points_sidecar(content, cell_routes_path(project, cell))
 
         svg_path = None
+        preview_status = "not_requested"
+        preview_error = None
         if create_preview:
             svg_path = cell_svg_path(project, cell)
-            # Routed layouts need the router backend; placement-only layouts can
-            # use the simpler GDS/SVG preview path.
-            if layout_has_links(content):
+            try:
                 create_routed_layout_svg(
                     content,
                     svg_path,
@@ -748,8 +752,11 @@ def save_layout():
                     technology_manifest_path=technology_manifest_path_for_project(project),
                     prefer_full_gds=prefer_full_gds_for_session(session),
                 )
-            else:
-                create_layout_svg_from_gds(content, svg_path, pdk_registry=current_pdk_registry(), project_dir=project_root(project))
+                preview_status = "generated"
+            except RouterStackUnavailable as e:
+                preview_status = "skipped"
+                preview_error = str(e)
+                svg_path = None
 
         record_action('layout.save', project=project, cell=cell, detail={"bytes": len(content), "svg": svg_path})
         return jsonify({
@@ -758,7 +765,9 @@ def save_layout():
             "cell": cell,
             "path": save_path,
             "svg_path": svg_path,
-            "svg_url": url_for('get_layout_svg', project_name=project, cell_name=cell) if svg_path else None
+            "svg_url": url_for('get_layout_svg', project_name=project, cell_name=cell) if svg_path else None,
+            "preview_status": preview_status,
+            "preview_error": preview_error
         }), 200
 
     except Exception as e:
diff --git a/database/admin/layout/MZM_TX/MZM_TX.svg b/database/admin/layout/MZM_TX/MZM_TX.svg
deleted file mode 100644
index 82ffe06..0000000
--- a/database/admin/layout/MZM_TX/MZM_TX.svg
+++ /dev/null
@@ -1,956 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="26541.9" height="7987.9" viewBox="-1210.45 2793.55 26541.9 7987.9">
-<defs>
-<style type="text/css">
-.l259d0 {stroke: #875692; fill: #875692; fill-opacity: 0.5;}
-.l100d160 {stroke: #F38400; fill: #F38400; fill-opacity: 0.5;}
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-.l1003t0 {stroke: none; fill: #C2B280;}
-</style>
-<g id="PIN_PS_L1000_1453">
-<polygon id="000001A660E0ED00" class="l173d0" points="0,95 10000,95 10000,45 0,45"/>
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-<use transform="translate(3300 -6300)" xlink:href="#Spliter_1x4"/>
-<use transform="translate(7500 -4600)" xlink:href="#MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603"/>
-<use transform="translate(0 -9200) rotate(180)" xlink:href="#EC_SiN400_1310_0p5dB_L935_A0_QY_202604"/>
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\ No newline at end of file
diff --git a/database/admin/layout/MZM_TX/MZM_TX.yml b/database/admin/layout/MZM_TX/MZM_TX.yml
deleted file mode 100644
index 6fdd59d..0000000
--- a/database/admin/layout/MZM_TX/MZM_TX.yml
+++ /dev/null
@@ -1,102 +0,0 @@
-# =============================================
-# mxPIC Cell/Project Definition File
-# =============================================
-schema_version: "2.0.0"
-kind: cell
-coordinate_system: gds_y_up
-canvas_size:
-  width: 5000
-  height: 5000
-project: MZM_TX
-name: MZM_TX
-type: project
-version: "1.0.0"
-
-# 1. External Ports (How this cell connects to the outside world)
-pins: []
-
-# 2. Instances (The sub-components dropped onto this canvas)
-instances:
-  Spliter_1x4:
-    component: Spliter_1x4
-    x: 330.0
-    y: -630.0
-    rotation: 0.0
-    flip: 0
-    flop: 0
-    mirror: false
-    settings:
-    length:
-
-  MZM_1:
-    component: Silterra/EMO1_2ML_CU_Al_RDL/composites/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603
-    x: 750.0
-    y: -460.0
-    rotation: 0.0
-    flip: 0
-    flop: 0
-    mirror: false
-    settings:
-    length:
-
-  EC_1:
-    component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604
-    x: 0.0
-    y: -920.0
-    rotation: 180.0
-    flip: 0
-    flop: 0
-    mirror: false
-    settings:
-    length:
-
-elements:
-  anchor_2:
-    type: anchor
-    x: 470.0
-    y: -840.0
-    angle: 0.0
-    pin_number: 1
-    pitch: 10
-    layer: WG_CORE
-    width: 0.5
-    description: ""
-    pins:
-      - name: anchor_2_a1
-        role: a1
-      - name: anchor_2_b1
-        role: b1
-
-# 3. Bundles (Grouped links for multi-bus/parallel routing)
-bundles:
-  output_bus:
-    routing_type: euler_bend
-    links:
-      - from: MZM_1:a1
-        to: Spliter_1x4:OutUp_io2
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: Spliter_1x4:OutUp_io1
-        to: MZM_1:a2
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: anchor_2:anchor_2_b1
-        to: EC_1:a1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: anchor_2:anchor_2_a1
-        to: Spliter_1x4:Input_io1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
\ No newline at end of file
diff --git a/database/admin/layout/MZM_TX/Spliter_1x4.yml b/database/admin/layout/MZM_TX/Spliter_1x4.yml
deleted file mode 100644
index 13bddcb..0000000
--- a/database/admin/layout/MZM_TX/Spliter_1x4.yml
+++ /dev/null
@@ -1,192 +0,0 @@
-# =============================================
-# mxPIC Cell/Project Definition File
-# =============================================
-schema_version: "2.0.0"
-kind: cell
-coordinate_system: gds_y_up
-canvas_size:
-  width: 500
-  height: 500
-project: MZM_TX
-name: Spliter_1x4
-type: composite
-version: "1.0.0"
-
-# 1. External Ports (How this cell connects to the outside world)
-pins:
-- name: Input_io1
-  layer: WG_CORE
-  element: Input
-  pin: io1
-  x: 10.0
-  y: -110.0
-  angle: 180.0
-  width: 0.5
-- name: OutUp_io1
-  layer: WG_CORE
-  element: OutUp
-  pin: io1
-  x: 335.0
-  y: -20.0
-  angle: 90.0
-  width: 0.5
-- name: OutUp_io2
-  layer: WG_CORE
-  element: OutUp
-  pin: io2
-  x: 325.0
-  y: -20.0
-  angle: 90.0
-  width: 0.5
-- name: port_4_io1
-  layer: WG_CORE
-  element: port_4
-  pin: io1
-  x: 350.0
-  y: -180.0
-  angle: 0.0
-  width: 0.5
-
-# 2. Instances (The sub-components dropped onto this canvas)
-instances:
-  MMI_2:
-    component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
-    x: 90.0
-    y: -110.0
-    rotation: 0.0
-    flip: 0
-    flop: 0
-    mirror: false
-    settings:
-    length:
-
-  MMI_3:
-    component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
-    x: 230.0
-    y: -90.0
-    rotation: 0.0
-    flip: 0
-    flop: 0
-    mirror: false
-    settings:
-    length:
-
-elements:
-  Input:
-    type: port
-    x: 10.0
-    y: -110.0
-    angle: 0.0
-    pin_number: 1
-    pitch: 10
-    layer: WG_CORE
-    width: 0.5
-    description: ""
-    pins:
-      - name: Input_io1
-        role: io1
-  OutUp:
-    type: port
-    x: 330.0
-    y: -20.0
-    angle: -90.0
-    pin_number: 2
-    pitch: 10
-    layer: WG_CORE
-    width: 0.5
-    description: ""
-    pins:
-      - name: OutUp_io1
-        role: io1
-      - name: OutUp_io2
-        role: io2
-  port_4:
-    type: port
-    x: 350.0
-    y: -180.0
-    angle: 180.0
-    pin_number: 1
-    pitch: 10
-    layer: WG_CORE
-    width: 0.5
-    description: ""
-    pins:
-      - name: port_4_io1
-        role: io1
-  anchor_1:
-    type: anchor
-    x: 250.0
-    y: -150.0
-    angle: 90.0
-    pin_number: 1
-    pitch: 10
-    layer: WG_CORE
-    width: 0.5
-    description: ""
-    pins:
-      - name: anchor_1_a1
-        role: a1
-      - name: anchor_1_b1
-        role: b1
-
-# 3. Bundles (Grouped links for multi-bus/parallel routing)
-bundles:
-  output_bus:
-    routing_type: euler_bend
-    links:
-      - from: MMI_2:a1
-        to: Input:Input_io1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: MMI_3:a1
-        to: MMI_2:b1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: MMI_3:b1
-        to: OutUp:OutUp_io1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: MMI_3:b1
-        to: OutUp:OutUp_io2
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: MMI_3:b2
-        to: OutUp:OutUp_io1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: MMI_2:b2
-        to: anchor_1:anchor_1_b1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: anchor_1:anchor_1_a1
-        to: port_4:port_4_io1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
-      - from: anchor_1:anchor_1_a1
-        to: anchor_1:anchor_1_b1
-        xsection: strip
-        family: optical
-        width: 0.45
-        radius: 10
-        routing_type: euler_bend
\ No newline at end of file
diff --git a/database/admin/layout/MZM_TX/canvas_1.svg b/database/admin/layout/MZM_TX/canvas_1.svg
deleted file mode 100644
index 28bba15..0000000
--- a/database/admin/layout/MZM_TX/canvas_1.svg
+++ /dev/null
@@ -1,69 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="2474.175" height="2076.925" viewBox="695.5375 1098.5375 2474.175 2076.925">
-<defs>
-<style type="text/css">
-.l275d0 {stroke: #654522; fill: #654522; fill-opacity: 0.5;}
-.l23d0 {stroke: #C2B280; fill: #C2B280; fill-opacity: 0.5;}
-.l101d251 {stroke: #848482; fill: #848482; fill-opacity: 0.5;}
-.l263d0 {stroke: #C2B280; fill: #C2B280; fill-opacity: 0.5;}
-</style>
-<g id="1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2">
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+<use transform="translate(5572 -18883)" xlink:href="#1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2"/>
+<use transform="translate(6892 -17975)" xlink:href="#1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2_6"/>
 </g>
 </svg>
\ No newline at end of file
diff --git a/database/admin/layout/mxpic_project_1/mxpic_project_1.yml b/database/admin/layout/mxpic_project_1/mxpic_project_1.yml
new file mode 100644
index 0000000..8512327
--- /dev/null
+++ b/database/admin/layout/mxpic_project_1/mxpic_project_1.yml
@@ -0,0 +1,89 @@
+# =============================================
+# mxPIC Cell/Project Definition File
+# =============================================
+schema_version: "2.0.0"
+kind: cell
+coordinate_system: gds_y_up
+canvas_size:
+  width: 5000
+  height: 5000
+project: mxpic_project_1
+name: mxpic_project_1
+type: project
+version: "1.0.0"
+
+# 1. External Ports (How this cell connects to the outside world)
+pins:
+- name: port_io1
+  layer: WG_CORE
+  element: port
+  pin: io1
+  x: 50.0
+  y: -150.0
+  angle: 180.0
+  width: 0.5
+
+# 2. Instances (The sub-components dropped onto this canvas)
+instances:
+  MMI_1:
+    component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
+    x: 557.2
+    y: -1888.3
+    rotation: 0.0
+    flip: 0
+    flop: 0
+    mirror: false
+    settings:
+    length:
+
+  MMI_2:
+    component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
+    x: 689.2
+    y: -1797.5
+    rotation: 0.0
+    flip: 0
+    flop: 0
+    mirror: false
+    settings:
+    length:
+
+elements:
+  port:
+    type: port
+    x: 50.0
+    y: -150.0
+    angle: 180.0
+    pin_number: 1
+    pitch: 10
+    layer: WG_CORE
+    width: 0.5
+    description: ""
+    pins:
+      - name: port_io1
+        role: io1
+  port:
+    type: port
+    x: 50.0
+    y: -150.0
+    angle: 0.0
+    pin_number: 1
+    pitch: 10
+    layer: WG_CORE
+    width: 0.5
+    description: ""
+    pins:
+      - name: port_io1
+        role: io1
+
+# 3. Bundles (Grouped links for multi-bus/parallel routing)
+bundles:
+  output_bus:
+    routing_type: euler_bend
+    links:
+      - from: MMI_1:b1
+        to: MMI_2:a1
+        xsection: strip
+        family: optical
+        width: 0.45
+        radius: 10
+        routing_type: euler_bend
\ No newline at end of file
diff --git a/database/mxpic_data.db b/database/mxpic_data.db
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QezTxJJlFR6UyO~c0D=z`2LJ#7

diff --git a/docs/superpowers/plans/2026-05-31-required-mxpic-router-stack.md b/docs/superpowers/plans/2026-05-31-required-mxpic-router-stack.md
new file mode 100644
index 0000000..bb8a36d
--- /dev/null
+++ b/docs/superpowers/plans/2026-05-31-required-mxpic-router-stack.md
@@ -0,0 +1,330 @@
+# Required mxpic_router Stack Implementation Plan
+
+> **For agentic workers:** REQUIRED SUB-SKILL: Use superpowers:subagent-driven-development (recommended) or superpowers:executing-plans to implement this plan task-by-task. Steps use checkbox (`- [ ]`) syntax for tracking.
+
+**Goal:** Make `mxpic_router` plus its Nazca/gdstk/route backend stack mandatory, and route all Build Layout and Build GDS generation through it.
+
+**Architecture:** Add a focused backend dependency gate module and make server startup fail before Flask launches when the router stack is incomplete. Keep `routed_layout_preview.py` as the single preview builder and simplify `gds_builder.py` so the production GDS path delegates to `mxpic_router` without silent fallback.
+
+**Tech Stack:** Python Flask backend, sibling `mxpic_router`, Nazca, gdstk, `mxpic_forge` route backend, Node static regression tests.
+
+---
+
+## File Structure
+
+- Create `backend/router_dependency.py`: one responsibility, validate and expose the required router stack.
+- Modify `backend/server.py`: import dependency gate, run it before `app.run`, and always call `create_routed_layout_svg` for previews.
+- Modify `backend/gds_builder.py`: make `_build_with_mxpic_router` the only production builder path.
+- Modify `tests/layout-backend-static.test.js`: update static assertions to the new required-router contract.
+- Modify `GDS_SVG_GENERATION_LOGIC.md`: replace the two Build Layout branches with one unified router path.
+- Modify `README.md` and `INTRANET_DEPLOYMENT.md`: document simultaneous EDA/router deployment.
+
+## Task 1: Static Tests For Required Router Contract
+
+**Files:**
+- Modify: `tests/layout-backend-static.test.js`
+
+- [ ] **Step 1: Write failing assertions**
+
+Replace the old `server.py` assertions around `create_layout_svg_from_gds` and `create_routed_layout_svg` with assertions that:
+
+```javascript
+assert(
+  fs.existsSync(path.join(backendDir, 'router_dependency.py')),
+  'backend/router_dependency.py should validate required mxpic_router runtime dependencies'
+);
+assert(
+  serverPy.includes('from router_dependency import require_router_stack') &&
+    serverPy.includes('require_router_stack()'),
+  'server startup should check the full mxpic_router stack before launching Flask'
+);
+assert(
+  !serverPy.includes('create_layout_svg_from_gds'),
+  'save-layout route should not use the legacy gdstk-only preview builder'
+);
+assert(
+  serverPy.includes('create_routed_layout_svg') &&
+    !serverPy.includes('if layout_has_links(content):'),
+  'save-layout route should always use routed preview generation through mxpic_router'
+);
+```
+
+Add assertions for `router_dependency.py`:
+
+```javascript
+const routerDependencyPy = fs.readFileSync(path.join(backendDir, 'router_dependency.py'), 'utf8');
+assert(
+  routerDependencyPy.includes('def require_router_stack') &&
+    routerDependencyPy.includes('importlib.import_module("gdstk")') &&
+    routerDependencyPy.includes('importlib.import_module("nazca")') &&
+    routerDependencyPy.includes('mxpic_router.builder') &&
+    routerDependencyPy.includes('_import_mxpic_forge_route'),
+  'router dependency gate should validate mxpic_router, Nazca, gdstk, and route backend imports'
+);
+```
+
+Replace the old GDS fallback assertions with:
+
+```javascript
+assert(
+  gdsBuilderPy.includes('return _build_with_mxpic_router(') &&
+    !gdsBuilderPy.includes('return _build_with_gdstk') &&
+    !gdsBuilderPy.includes('return _build_with_nazca'),
+  'Build GDS should use mxpic_router as the only production builder'
+);
+```
+
+- [ ] **Step 2: Run the focused test to verify RED**
+
+Run: `node tests/layout-backend-static.test.js`
+
+Expected: FAIL because `router_dependency.py` does not exist, `server.py` still imports `create_layout_svg_from_gds`, and `gds_builder.py` still contains fallback returns.
+
+## Task 2: Add Router Dependency Gate
+
+**Files:**
+- Create: `backend/router_dependency.py`
+- Modify: `backend/server.py`
+
+- [ ] **Step 1: Implement `backend/router_dependency.py`**
+
+Create a small module with:
+
+```python
+import importlib
+import os
+import sys
+from dataclasses import dataclass, field
+from typing import List
+
+
+@dataclass
+class RouterStackStatus:
+    ok: bool
+    router_root: str
+    checked: List[str] = field(default_factory=list)
+
+
+def ensure_router_path() -> str:
+    router_root = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "mxpic_router"))
+    if os.path.isdir(router_root) and router_root not in sys.path:
+        sys.path.insert(0, router_root)
+    return router_root
+
+
+def require_router_stack() -> RouterStackStatus:
+    router_root = ensure_router_path()
+    checked = []
+    missing = []
+
+    for module_name, label in (
+        ("mxpic_router", "mxpic_router"),
+        ("nazca", "nazca"),
+        ("gdstk", "gdstk"),
+    ):
+        try:
+            importlib.import_module(module_name)
+            checked.append(label)
+        except Exception as exc:
+            missing.append(f"{label}: {exc}")
+
+    try:
+        router_builder = importlib.import_module("mxpic_router.builder")
+        route_factory = getattr(router_builder, "_import_mxpic_forge_route")
+        route_factory()
+        checked.append("mxpic_forge Route")
+    except Exception as exc:
+        missing.append(f"mxpic_forge Route: {exc}")
+
+    if missing:
+        details = "; ".join(missing)
+        raise RuntimeError(
+            "Required mxpic_router runtime stack is unavailable. "
+            "Deploy mxpic_EDA together with the matched mxpic_router and mxpic_forge checkouts, "
+            f"then install nazca and gdstk. Details: {details}"
+        )
+
+    return RouterStackStatus(ok=True, router_root=router_root, checked=checked)
+```
+
+- [ ] **Step 2: Wire startup check in `backend/server.py`**
+
+Import:
+
+```python
+from router_dependency import require_router_stack
+```
+
+Before `app.run(...)` in the `if __name__ == '__main__':` block:
+
+```python
+    router_status = require_router_stack()
+    print(f"Verified mxpic_router stack: {', '.join(router_status.checked)}")
+```
+
+- [ ] **Step 3: Run focused test to verify progress**
+
+Run: `node tests/layout-backend-static.test.js`
+
+Expected: still FAIL because preview and GDS builder branches have not been unified yet.
+
+## Task 3: Unify Build Layout Preview Path
+
+**Files:**
+- Modify: `backend/server.py`
+
+- [ ] **Step 1: Remove legacy preview imports**
+
+Change imports from:
+
+```python
+from layout_preview import create_layout_svg_from_gds
+from routed_layout_preview import create_routed_layout_svg, layout_has_links
+```
+
+to:
+
+```python
+from routed_layout_preview import create_routed_layout_svg
+```
+
+- [ ] **Step 2: Replace preview branch**
+
+Replace the `if layout_has_links(content): ... else: ...` block inside
+`save_layout` with one unconditional call:
+
+```python
+            create_routed_layout_svg(
+                content,
+                svg_path,
+                pdk_root=current_pdk_root(),
+                project_dir=project_root(project),
+                technology_manifest_path=technology_manifest_path_for_project(project),
+                prefer_full_gds=prefer_full_gds_for_session(session),
+            )
+```
+
+- [ ] **Step 3: Run focused test**
+
+Run: `node tests/layout-backend-static.test.js`
+
+Expected: still FAIL only on GDS builder fallback assertions.
+
+## Task 4: Unify Build GDS Builder Path
+
+**Files:**
+- Modify: `backend/gds_builder.py`
+
+- [ ] **Step 1: Simplify production builder**
+
+Change `build_project_gds` so after `_load_project_cells` validation it returns
+only `_build_with_mxpic_router(...)`:
+
+```python
+    cells = _load_project_cells(project_dir)
+    if not cells:
+        raise ValueError("No saved cell YAML files found for this project")
+
+    return _build_with_mxpic_router(
+        project_dir,
+        output_path,
+        pdk_public_root,
+        technology_manifest_path,
+        prefer_full_gds,
+    )
+```
+
+- [ ] **Step 2: Remove unreachable fallback code**
+
+Delete `_cells_have_links`, `_cells_have_elements`, `_build_with_gdstk`,
+`_import_public_gds`, `_build_with_nazca`, `_build_nazca_element_cells`,
+`_build_nazca_element_cell`, `_element_port_offset`, `_element_pin_names`,
+`_safe_pin_name`, `_safe_cell_name`, `_library_cell_by_name`, `_int`, and
+`_number` if no remaining code references them.
+
+Remove unused imports such as `math` and `PdkRegistry`.
+
+- [ ] **Step 3: Run focused test**
+
+Run: `node tests/layout-backend-static.test.js`
+
+Expected: PASS.
+
+## Task 5: Update Logic And Release Documentation
+
+**Files:**
+- Modify: `GDS_SVG_GENERATION_LOGIC.md`
+- Modify: `README.md`
+- Modify: `INTRANET_DEPLOYMENT.md`
+
+- [ ] **Step 1: Update logic path markdown**
+
+Rewrite Build Layout to describe:
+
+```text
+Click Build Layout -> handleBuildLayout -> /api/save-layout -> save_layout
+writes .yml -> create_routed_layout_svg -> mxpic_router.build_project_gds
+creates Nazca GDS -> gdstk reads temporary GDS and writes .svg
+```
+
+Rewrite Build GDS to describe:
+
+```text
+Click Build GDS -> /api/build-gds -> build_gds -> gds_builder.build_project_gds
+loads saved .yml files -> _build_with_mxpic_router -> mxpic_router creates
+nd.Cell objects and exports .gds
+```
+
+- [ ] **Step 2: Update release docs**
+
+Add a short note to `README.md` and `INTRANET_DEPLOYMENT.md`:
+
+```markdown
+### Required Router Stack
+
+`mxpic_EDA` must be deployed with the matched `mxpic_router` and `mxpic_forge`
+checkouts. The backend validates `mxpic_router`, Nazca, gdstk, and the route
+backend before launching the Flask server, so release and deploy these
+repositories together.
+```
+
+- [ ] **Step 3: Run docs/static test**
+
+Run: `node tests/layout-backend-static.test.js`
+
+Expected: PASS.
+
+## Task 6: Final Verification
+
+**Files:**
+- Verify only.
+
+- [ ] **Step 1: Run focused backend contract test**
+
+Run: `node tests/layout-backend-static.test.js`
+
+Expected: PASS.
+
+- [ ] **Step 2: Run all Node static tests**
+
+Run each test script:
+
+```powershell
+node tests\account-pdk-access-static.test.js
+node tests\canvas-generation-wiring.test.js
+node tests\canvas-helpers.test.js
+node tests\canvas-static-route.test.js
+node tests\gds-download-static.test.js
+node tests\layout-backend-static.test.js
+node tests\layout-ui-wiring.test.js
+node tests\project-load-static.test.js
+```
+
+Expected: all scripts exit code 0.
+
+- [ ] **Step 3: Check git status**
+
+Run: `git status --short`
+
+Expected: modified/added files are limited to the router-stack implementation,
+the plan, docs, and existing pre-task changes.
diff --git a/docs/superpowers/plans/2026-06-01-pdk-root-technology-migration.md b/docs/superpowers/plans/2026-06-01-pdk-root-technology-migration.md
new file mode 100644
index 0000000..750ebf9
--- /dev/null
+++ b/docs/superpowers/plans/2026-06-01-pdk-root-technology-migration.md
@@ -0,0 +1,93 @@
+# PDK Root Technology Migration Implementation Plan
+
+> **For agentic workers:** REQUIRED SUB-SKILL: Use superpowers:subagent-driven-development (recommended) or superpowers:executing-plans to implement this plan task-by-task. Steps use checkbox (`- [ ]`) syntax for tracking.
+
+**Goal:** Make `opt_pdk_public/foundries` and `opt_pdk_atlas/foundries` the single source of truth for both component PDK assets and `technology.yml` manifests, then remove the redundant `mxpic/` folder from `mxpic_EDA`.
+
+**Architecture:** The backend resolves a role-scoped PDK root from the current Flask session. Technology listing, manifest reads, project-scoped library browsing, SVG preview, and GDS export all use that same root. A directory directly under `<role_pdk_root>/<foundry>` is treated as a technology only when it contains `technology.yml`.
+
+**Tech Stack:** Flask backend, local YAML manifests, PowerShell/Node static tests, `mxpic_router`/Nazca build path.
+
+---
+
+### Task 1: Regression Tests for New PDK Source of Truth
+
+**Files:**
+- Modify: `tests/layout-backend-static.test.js`
+
+- [ ] **Step 1: Write the failing test**
+
+Add assertions that `backend/server.py` no longer defines `EDA_PDK_ROOT`/`YML_PATH`, does not reference `mxpic/PDKs`, lists technologies from `current_pdk_root()`, checks for `technology.yml`, and reads manifests from the active role PDK root.
+
+- [ ] **Step 2: Run test to verify it fails**
+
+Run: `node tests/layout-backend-static.test.js`
+
+Expected before implementation: FAIL because the backend still scans `EDA_PDK_ROOT`.
+
+### Task 2: Backend Migration
+
+**Files:**
+- Modify: `backend/server.py`
+
+- [ ] **Step 1: Update root helpers**
+
+Remove `PDK_PUBLIC_ROOT`, `EDA_PDK_ROOT`, and `YML_PATH` from active path configuration. Add a helper that safely builds `<current_pdk_root>/<foundry>/<technology>/technology.yml`.
+
+- [ ] **Step 2: Update technology APIs**
+
+Change `/api/technologies` and `/api/technologies/<foundry>/<technology>/manifest` to use `current_pdk_root()`. Only return technology folders containing `technology.yml`.
+
+- [ ] **Step 3: Update build-time manifest lookup**
+
+Change `technology_manifest_path_for_project(project)` to read the project `foundry/technology` ID and return the manifest path under the active role PDK root.
+
+### Task 3: Documentation and Static Contract Updates
+
+**Files:**
+- Modify: `README.md`
+- Modify: `INTRANET_DEPLOYMENT.md`
+- Modify: `PDK_TECHNOLOGY_XSECTION_LOADING.md`
+- Modify: `GDS_SVG_GENERATION_LOGIC.md`
+- Modify: `tests/layout-backend-static.test.js`
+
+- [ ] **Step 1: Update docs**
+
+Replace old `mxpic/PDKs` source-of-truth language with role PDK root language.
+
+- [ ] **Step 2: Keep tests aligned**
+
+Remove assertions that require `mxpic/PDKs/Silterra/.../technology.yml` to exist inside `mxpic_EDA`.
+
+### Task 4: Remove Redundant EDA PDK Folder
+
+**Files:**
+- Delete: `mxpic/`
+
+- [ ] **Step 1: Verify target path**
+
+Run: `Resolve-Path mxpic` and confirm it resolves inside `D:\mxpic\mxpic_EDA`.
+
+- [ ] **Step 2: Delete folder**
+
+Run: `Remove-Item -LiteralPath D:\mxpic\mxpic_EDA\mxpic -Recurse -Force`.
+
+### Task 5: Verification
+
+**Files:**
+- Test: `tests/*.test.js`
+
+- [ ] **Step 1: Run focused tests**
+
+Run: `node tests/layout-backend-static.test.js`
+
+- [ ] **Step 2: Run full static suite**
+
+Run each `tests/*.test.js` file with Node.
+
+- [ ] **Step 3: Check old references**
+
+Run: `rg -n "EDA_PDK_ROOT|YML_PATH|mxpic/PDKs|mxpic\\\\PDKs" backend frontend tests README.md INTRANET_DEPLOYMENT.md GDS_SVG_GENERATION_LOGIC.md PDK_TECHNOLOGY_XSECTION_LOADING.md`
+
+Expected: no active-code references to the deleted internal PDK root.
+
diff --git a/frontend/canvas.html b/frontend/canvas.html
index 7f87a9d..9acde81 100644
--- a/frontend/canvas.html
+++ b/frontend/canvas.html
@@ -6235,6 +6235,9 @@ ${bundlesBlock}`;
 
           const result = await response.json();
           addLog('Successfully saved: ' + result.path);
+          if (result.preview_error) {
+            addLog('Preview skipped: ' + result.preview_error);
+          }
           if (result.svg_url) {
             completeBuildProgress('Layout ready');
             openLayoutPreview(activePage.name, result.svg_url, calculateLayoutBounds(activePage));
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603.yml
deleted file mode 100644
index e084ebb..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603.yml
+++ /dev/null
@@ -1,76 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: New PDK cell for High-speed tunable MZI with p-i-n phase shifer
-ports:
-  a1:
-    x: 0.0
-    y: 4.475
-    a: 180.0
-    width: 0.7
-  a2:
-    x: 0.0
-    y: -4.475
-    a: 180.0
-    width: 0.7
-  b1:
-    x: 1660.0
-    y: 4.475
-    a: 360.0
-    width: 0.7
-  b2:
-    x: 1660.0
-    y: -4.475
-    a: 360.0
-    width: 0.7
-  pin_p:
-    x: 1660.0
-    y: 25.0
-    a: 0.0
-    width: 10.0
-  pin_n:
-    x: 1660.0
-    y: 55.0
-    a: 0.0
-    width: 10.0
-  ht_s:
-    x: 1660.0
-    y: -25.0
-    a: 0.0
-    width: 10.0
-  ht_g:
-    x: 1660.0
-    y: -55.0
-    a: 0.0
-    width: 10.0
-  a0:
-    x: 0.0
-    y: 0.0
-    a: 180.0
-    width: 0.0
-  b0:
-    x: 0.0
-    y: 0.0
-    a: 0.0
-    width: 0.0
-time: 20260515-232153
-box_size:
-- 1663.0
-- 149.0
-file_size: 95.98 KB
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603_BB.svg
deleted file mode 100644
index 64154b1..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603_BB.svg
+++ /dev/null
@@ -1,34 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="18318.85" height="3155.35" viewBox="-836.175 -1437.675 18318.85 3155.35">
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-.l1200d0 {stroke: #F38400; fill: #F38400; fill-opacity: 0.5;}
-.l1205d0 {stroke: #008856; fill: #008856; fill-opacity: 0.5;}
-.l1001t0 {stroke: none; fill: #A1CAF1;}
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-</defs>
-<rect x="-836.175" y="-1437.675" width="18318.85" height="3155.35" fill="white" stroke="none"/>
-<g id="MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603" transform="scale(1 -1)">
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-<text id="00000155545DE810" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(16600 250) scale(1 -1)">pin_p</text>
-<text id="00000155545DE420" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(16600 550) scale(1 -1)">pin_n</text>
-<text id="00000155545DE150" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(16600 -250) scale(1 -1)">ht_s</text>
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-<text id="00000155545DDCD0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(0 0) scale(1 -1)">a0</text>
-<text id="00000155545DD460" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(0 0) scale(1 -1)">b0</text>
-</g>
-</svg>
\ No newline at end of file
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303.yml
deleted file mode 100644
index 3b8b216..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 1600G operation, labeling A1
-ports:
-  g1:
-    x: -120.0
-    y: 225.0
-    a: 360.0
-    width: 130.0
-  g1b:
-    x: -200.0
-    y: 225.0
-    a: 180.0
-    width: 130.0
-  s1:
-    x: -120.0
-    y: 75.0
-    a: 360.0
-    width: 130.0
-  s1b:
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-    y: 75.0
-    a: 180.0
-    width: 130.0
-  s2:
-    x: -120.0
-    y: -75.0
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-    width: 130.0
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-    y: -75.0
-    a: 180.0
-    width: 130.0
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-    width: 130.0
-  g2b:
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-    y: -225.0
-    a: 180.0
-    width: 130.0
-  a0:
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-    y: 0.0
-    a: 0.0
-    width: None
-  b0:
-    x: -120.0
-    y: 0.0
-    a: 180.0
-    width: None
-  a1:
-    x: 342.0
-    y: -123.42
-    a: 0.0
-    width: 1.0
-  b1:
-    x: 1959.6
-    y: 170.525
-    a: 180.0
-    width: 1.0
-  b2:
-    x: 1959.6
-    y: 179.475
-    a: 180.0
-    width: 1.0
-  ep2:
-    x: 2648.0
-    y: 205.25
-    a: 360.0
-    width: 10.0
-  en2:
-    x: 2588.0
-    y: 231.75
-    a: 360.0
-    width: 10.0
-  vbias:
-    x: 2943.92
-    y: 121.0
-    a: 180.0
-    width: 10.0
-  vres:
-    x: 2943.5
-    y: 0.0
-    a: 0.0
-    width: 30.0
-time: 20260515-233028
-box_size:
-- 3463.5
-- 780.0
-file_size: 1474.03 KB
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303_BB.svg
deleted file mode 100644
index 958c9f5..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA1_QY_v1_20260303_BB.svg
+++ /dev/null
@@ -1,48 +0,0 @@
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deleted file mode 100644
index 999bd5d..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA2_QY_v1_20260303_BB.svg
deleted file mode 100644
index 0467430..0000000
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+++ /dev/null
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deleted file mode 100644
index d18b454..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA3_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 1600G operation, labeling A3
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deleted file mode 100644
index a8ffd6f..0000000
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deleted file mode 100644
index 2c0d516..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA4_QY_v1_20260303_BB.svg
deleted file mode 100644
index c33059b..0000000
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deleted file mode 100644
index 00c84f9..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeA5_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeA5_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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deleted file mode 100644
index 735f9df..0000000
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deleted file mode 100644
index aa8eccf..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE1_QY_v1_20260303_BB.svg
deleted file mode 100644
index 7a7a8cf..0000000
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+++ /dev/null
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deleted file mode 100644
index 02ca117..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeE2_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 1600G operation, labeling E2
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deleted file mode 100644
index 192a691..0000000
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deleted file mode 100644
index a9e527c..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE3_QY_v1_20260303_BB.svg
deleted file mode 100644
index 56042c1..0000000
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deleted file mode 100644
index 70376b7..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeE4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeE4_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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deleted file mode 100644
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deleted file mode 100644
index 9261bb5..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG1_QY_v1_20260303_BB.svg
deleted file mode 100644
index 10598b6..0000000
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+++ /dev/null
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deleted file mode 100644
index ad1829b..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 1600G operation, labeling G2
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deleted file mode 100644
index 82063f8..0000000
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deleted file mode 100644
index d9d261c..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
-designer: Qin Yue
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-- 3458.5
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG3_QY_v1_20260303_BB.svg
deleted file mode 100644
index 937cbb2..0000000
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+++ /dev/null
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deleted file mode 100644
index cf18687..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeG4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeG4_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeG4_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 1600G operation, labeling G4
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deleted file mode 100644
index 4b77d5e..0000000
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deleted file mode 100644
index 6aefb63..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 1600G operation, labeling Z1
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ1_QY_v1_20260303_BB.svg
deleted file mode 100644
index 28ed6ca..0000000
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+++ /dev/null
@@ -1,48 +0,0 @@
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deleted file mode 100644
index 6d90d83..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ2_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeZ2_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 1600G operation, labeling Z2
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deleted file mode 100644
index 03a6a2e..0000000
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deleted file mode 100644
index 7667b22..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_1600G_L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ3_QY_v1_20260303_BB.svg
deleted file mode 100644
index 514d46d..0000000
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+++ /dev/null
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deleted file mode 100644
index 84619db..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_1600G_L3000_GSSG_TRAIL_TypeZ4_QY_v1_20260303/MZM_1600G_L3000_GSSG_TRAIL_TypeZ4_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-designer: Qin Yue
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deleted file mode 100644
index 20bc7b8..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303.yml
deleted file mode 100644
index cfc5713..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
-designer: Qin Yue
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303_BB.svg
deleted file mode 100644
index 176ac34..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR1_QY_v1_20260303_BB.svg
+++ /dev/null
@@ -1,48 +0,0 @@
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303.yml
deleted file mode 100644
index 64fb553..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeR2_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 800G operation, labeling R2
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deleted file mode 100644
index 4823ffc..0000000
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deleted file mode 100644
index 0bad9a9..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT1_QY_v1_20260303_BB.svg
deleted file mode 100644
index 0691158..0000000
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+++ /dev/null
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deleted file mode 100644
index e476616..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
-designer: Qin Yue
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deleted file mode 100644
index 8262308..0000000
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deleted file mode 100644
index 52ea57f..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT3_QY_v1_20260303_BB.svg
deleted file mode 100644
index 6362556..0000000
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deleted file mode 100644
index b507a30..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT4_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
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-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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deleted file mode 100644
index 15a0df2..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303.yml
deleted file mode 100644
index 1803f35..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeT5_QY_v1_20260303_BB.svg
deleted file mode 100644
index fb98974..0000000
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+++ /dev/null
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deleted file mode 100644
index 8e330b4..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeV1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeV1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 800G operation, labeling V1
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deleted file mode 100644
index eceeb0f..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303.yml
deleted file mode 100644
index 3a9f69f..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeV2_QY_v1_20260303_BB.svg
deleted file mode 100644
index a66302d..0000000
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+++ /dev/null
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deleted file mode 100644
index 727f162..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
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-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
-designer: Qin Yue
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deleted file mode 100644
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303.yml
deleted file mode 100644
index 63e525b..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW2_QY_v1_20260303_BB.svg
deleted file mode 100644
index d9f2c71..0000000
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+++ /dev/null
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deleted file mode 100644
index e9757b8..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW3_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW3_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
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deleted file mode 100644
index 12a702c..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303.yml
deleted file mode 100644
index 45cf5b1..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeW4_QY_v1_20260303_BB.svg
deleted file mode 100644
index f2ce22e..0000000
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+++ /dev/null
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deleted file mode 100644
index d523155..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX1_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX1_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
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deleted file mode 100644
index 13cf1b0..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303.yml
deleted file mode 100644
index e382e35..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-designer: Qin Yue
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX2_QY_v1_20260303_BB.svg
deleted file mode 100644
index ca7c1c8..0000000
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+++ /dev/null
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deleted file mode 100644
index 0087a59..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX3_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX3_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeX3_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: new MZM desgin used for 800G operation, labeling X3
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deleted file mode 100644
index c1debc4..0000000
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deleted file mode 100644
index 5527c36..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: MZM_800G_L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX4_QY_v1_20260303_BB.svg
deleted file mode 100644
index 708cd3f..0000000
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+++ /dev/null
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deleted file mode 100644
index a0135af..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/composite/Mach_Zender_modulators/MZM_800G_L3000_GSSG_TRAIL_TypeX5_QY_v1_20260303/MZM_800G_L3000_GSSG_TRAIL_TypeX5_QY_v1_20260303.yml
+++ /dev/null
@@ -1,113 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: composite
-dependency:
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\multimode_interferometers\MMI1x2_ZKY
-- .\Silterra\EMO1_2ML_Cu_RDL\primitives\SiN_Si_convertors\SiN_Si_transition
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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-version: 1.0
-designer: Qin Yue
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deleted file mode 100644
index e8cbd1e..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/inductors/INDC_200pH_SiNPP_QY_202604/INDC_200pH_SiNPP_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/inductors/INDC_200pH_SiNPP_QY_202604/INDC_200pH_SiNPP_QY_202604.yml
deleted file mode 100644
index 3e5fefe..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/inductors/INDC_200pH_SiNPP_QY_202604/INDC_200pH_SiNPP_QY_202604.yml
+++ /dev/null
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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deleted file mode 100644
index 7e39c12..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/pads/RFPAD_GSSG_P625_QY_202604/RFPAD_GSSG_P625_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/pads/RFPAD_GSSG_P625_QY_202604/RFPAD_GSSG_P625_QY_202604.yml
deleted file mode 100644
index aed98d9..0000000
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+++ /dev/null
@@ -1,76 +0,0 @@
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-# Inside functions: N/A - declarative YAML metadata/configuration.
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-# -----------------------------------------------------------------------------
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deleted file mode 100644
index 85d5091..0000000
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deleted file mode 100644
index 10c0bb3..0000000
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+++ /dev/null
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/resistors/RES_30OHM_NPP_QY_202604/RES_30OHM_NPP_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/resistors/RES_30OHM_NPP_QY_202604/RES_30OHM_NPP_QY_202604.yml
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-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
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-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
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deleted file mode 100644
index f0c802d..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/electronics/resistors/RES_35OHM_NPP_QY_202604/RES_35OHM_NPP_QY_202604.yml
+++ /dev/null
@@ -1,76 +0,0 @@
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-# Inside functions: N/A - declarative YAML metadata/configuration.
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-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-time: 20260515-232035
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index a782e16..0000000
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deleted file mode 100644
index 18c873c..0000000
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+++ /dev/null
@@ -1,76 +0,0 @@
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-# Inside functions: N/A - declarative YAML metadata/configuration.
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-# Organization : OptiHK Limited
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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deleted file mode 100644
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+++ /dev/null
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deleted file mode 100644
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deleted file mode 100644
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deleted file mode 100644
index 93f596a..0000000
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+++ /dev/null
@@ -1,46 +0,0 @@
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index 32d81b8..0000000
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deleted file mode 100644
index 3b23c45..0000000
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+++ /dev/null
@@ -1,46 +0,0 @@
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-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
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deleted file mode 100644
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/bendings/Si_EUB_1310_H220_w380_2000_L50_QY_202604/Si_EUB_1310_H220_w380_2000_L50_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/bendings/Si_EUB_1310_H220_w380_2000_L50_QY_202604/Si_EUB_1310_H220_w380_2000_L50_QY_202604.yml
deleted file mode 100644
index 938bbf3..0000000
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+++ /dev/null
@@ -1,46 +0,0 @@
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-# Inside functions: N/A - declarative YAML metadata/configuration.
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-# Organization : OptiHK Limited
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deleted file mode 100644
index 89c1509..0000000
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deleted file mode 100644
index 2103cff..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604/EC_SiN400_1310_0p5dB_L935_A0_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604/EC_SiN400_1310_0p5dB_L935_A0_QY_202604.yml
deleted file mode 100644
index 2c07078..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604/EC_SiN400_1310_0p5dB_L935_A0_QY_202604.yml
+++ /dev/null
@@ -1,41 +0,0 @@
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-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-designer: Qin Yue
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-time: 20260515-232035
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604/EC_SiN400_1310_0p5dB_L935_A0_QY_202604_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604/EC_SiN400_1310_0p5dB_L935_A0_QY_202604_BB.svg
deleted file mode 100644
index 06e14f6..0000000
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deleted file mode 100644
index 5509b4a..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A8_QY_202604/EC_SiN400_1310_0p5dB_L935_A8_QY_202604.yml
+++ /dev/null
@@ -1,41 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-designer: Qin Yue
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-    a: 180.0
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-time: 20260515-232036
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-- 948.388
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A8_QY_202604/EC_SiN400_1310_0p5dB_L935_A8_QY_202604_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A8_QY_202604/EC_SiN400_1310_0p5dB_L935_A8_QY_202604_BB.svg
deleted file mode 100644
index c9364c0..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml
deleted file mode 100644
index 5ddb90a..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604.yml
+++ /dev/null
@@ -1,41 +0,0 @@
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-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-dependency: None
-maturity: development
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-designer: Qin Yue
-update_notes: New SiN edge couplers with high efficiency
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-    y: 0.0
-    a: 180.0
-    width: 0.0
-time: 20260515-232035
-box_size:
-- 646.0
-- 75.0
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_1p0dB_L635_A0_QY_202604/EC_SiN400_1310_1p0dB_L635_A0_QY_202604_BB.svg
deleted file mode 100644
index 48457a6..0000000
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deleted file mode 100644
index 7a556df..0000000
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+++ /dev/null
@@ -1,41 +0,0 @@
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-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-time: 20260515-232035
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deleted file mode 100644
index 55550d7..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2.yml
deleted file mode 100644
index 23b3aa1..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2.yml
+++ /dev/null
@@ -1,51 +0,0 @@
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-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
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-process: EMO1_2ML_Cu_RDL
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-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-- 87.0
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deleted file mode 100644
index db4f76c..0000000
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deleted file mode 100644
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+++ /dev/null
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-# Inside functions: N/A - declarative YAML metadata/configuration.
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-# -----------------------------------------------------------------------------
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-dependency: None
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-designer: Zhong Keyi
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deleted file mode 100644
index a8f05d9..0000000
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+++ /dev/null
@@ -1,63 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: PD_1310_Monitor_Si220_Ge500_NPN_XHN_202604
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
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-type: primitives
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-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/terminations/WG_TERM_SiN220_1310_w380_t150_QY_202606/WG_TERM_SiN220_1310_w380_t150_QY_202606.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/terminations/WG_TERM_SiN220_1310_w380_t150_QY_202606/WG_TERM_SiN220_1310_w380_t150_QY_202606.yml
deleted file mode 100644
index de1bd3e..0000000
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+++ /dev/null
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-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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deleted file mode 100644
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deleted file mode 100644
index f3d57c0..0000000
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+++ /dev/null
@@ -1,41 +0,0 @@
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-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: WG_TERM_SiN400_1310_w700_t150_QY_202606
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-center_wavelength: 1310
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/transitions/Si_Strip_Rib_TRX_w380/Si_Strip_Rib_TRX_w380.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/transitions/Si_Strip_Rib_TRX_w380/Si_Strip_Rib_TRX_w380.yml
deleted file mode 100644
index b20ba97..0000000
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+++ /dev/null
@@ -1,46 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
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-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: Silterra silicon to rib transition
-ports:
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-time: 20260515-232035
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deleted file mode 100644
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604.yml
deleted file mode 100644
index d6c2982..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604.yml
+++ /dev/null
@@ -1,46 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: Silicon doped heater dummy with 200 Ohm resistance
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-time: 20260515-232035
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604/HT_150R_SiPPP_L500_100OHM_DUMMY_QY_202604_BB.svg
deleted file mode 100644
index 70c2106..0000000
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deleted file mode 100644
index b57e3f1..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_QY_202604/HT_150R_SiPPP_L500_100OHM_QY_202604.yml
+++ /dev/null
@@ -1,67 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: HT_150R_SiPPP_L500_100OHM_QY_202604
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
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-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: Silicon doped heater with 200 Ohm resistance and around 14 mW Ppi for
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-time: 20260515-232035
-box_size:
-- 267.0
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_QY_202604/HT_150R_SiPPP_L500_100OHM_QY_202604_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_SiPPP_L500_100OHM_QY_202604/HT_150R_SiPPP_L500_100OHM_QY_202604_BB.svg
deleted file mode 100644
index c577bce..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L200_200OHM_QY_202604/HT_150R_TiN_L200_200OHM_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L200_200OHM_QY_202604/HT_150R_TiN_L200_200OHM_QY_202604.yml
deleted file mode 100644
index 0af15f4..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L200_200OHM_QY_202604/HT_150R_TiN_L200_200OHM_QY_202604.yml
+++ /dev/null
@@ -1,67 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: HT_150R_TiN_L200_200OHM_QY_202604
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: TiN heater with 200 Ohm resistance and around 10 mW Ppi for 1310 operation
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-ports:
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-    y: 0.0
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-    width: 0.38
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-    y: 0.0
-    a: 0.0
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-time: 20260515-232035
-box_size:
-- 327.0
-- 63.6
-file_size: 43.52 KB
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L200_200OHM_QY_202604/HT_150R_TiN_L200_200OHM_QY_202604_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L200_200OHM_QY_202604/HT_150R_TiN_L200_200OHM_QY_202604_BB.svg
deleted file mode 100644
index 5ad6113..0000000
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diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604.yml
deleted file mode 100644
index 7ea5cbd..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604.yml
+++ /dev/null
@@ -1,46 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: HT_150R_TiN_L500_200OHM_DUMMY_QY_202604
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
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-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: TiN heater dummy with 200 Ohm resistance
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-time: 20260515-232035
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-- 327.0
-- 63.6
-file_size: 54.65 KB
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604_BB.svg
deleted file mode 100644
index f812e86..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604/HT_150R_TiN_L500_200OHM_DUMMY_QY_202604_BB.svg
+++ /dev/null
@@ -1,22 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="3597" height="963" viewBox="-848.5 -516.5 3597 963">
-<defs>
-<style type="text/css">
-.l1200d0 {stroke: #F38400; fill: #F38400; fill-opacity: 0.5;}
-.l1205d0 {stroke: #008856; fill: #008856; fill-opacity: 0.5;}
-.l1001t0 {stroke: none; fill: #A1CAF1;}
-</style>
-</defs>
-<rect x="-848.5" y="-516.5" width="3597" height="963" fill="white" stroke="none"/>
-<g id="HT_150R_TiN_L500_200OHM_DUMMY_QY_202604" transform="scale(1 -1)">
-<polygon id="000001F928F2D0F0" class="l1200d0" points="-685,-283 2585,-283 2585,353 -685,353"/>
-<polygon id="000001F928F2CC20" class="l1205d0" points="-598.1,1.9 -601.9,1.9 -601.9,-1.9 -598.1,-1.9"/>
-<polygon id="000001F928F2DD30" class="l1205d0" points="2498.1,68.1 2501.9,68.1 2501.9,71.9 2498.1,71.9"/>
-<polygon id="000001F928F2D2B0" class="l1205d0" points="0,0 0,0 0,0 0,0"/>
-<polygon id="000001F928F2DC50" class="l1205d0" points="0,0 0,0 0,0 0,0"/>
-<text id="000001F923C38F90" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(-600 0) scale(1 -1)">a1</text>
-<text id="000001F923C38180" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(2500 70) scale(1 -1)">b1</text>
-<text id="000001F923C38570" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(0 0) scale(1 -1)">a0</text>
-<text id="000001F923C38CC0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(0 0) scale(1 -1)">b0</text>
-</g>
-</svg>
\ No newline at end of file
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/VOA_Si220_1310_L1050_QY_202603/VOA_Si220_1310_L1050_QY_202603.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/VOA_Si220_1310_L1050_QY_202603/VOA_Si220_1310_L1050_QY_202603.yml
deleted file mode 100644
index 62e724e..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/VOA_Si220_1310_L1050_QY_202603/VOA_Si220_1310_L1050_QY_202603.yml
+++ /dev/null
@@ -1,66 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: PDK component metadata describing photonic/electronic cell assets, pins, geometry, layers, and library classification.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-name: VOA_Si220_1310_L1050_QY_202603
-foundry: Silterra
-process: EMO1_2ML_Cu_RDL
-year: '2026'
-type: primitive
-dependency: None
-maturity: development
-tapeout_history:
-- run: Silterra_EMO1_2ML_Cu_RDL_2026_Q2
-  status: Pending testing
-center_wavelength: 1310
-version: 1.0
-designer: Qin Yue
-update_notes: New PDK of silicon based VOA
-ports:
-  a1:
-    x: -25.0
-    y: 0.0
-    a: 180.0
-    width: 0.38
-  a0:
-    x: -25.0
-    y: 0.0
-    a: 180.0
-    width: 0.38
-  b1:
-    x: 1025.0
-    y: -0.0
-    a: 360.0
-    width: 0.38
-  b0:
-    x: 1025.0
-    y: -0.0
-    a: 360.0
-    width: 0.38
-  n1:
-    x: 0.0
-    y: -7.0
-    a: 180.0
-    width: 5.0
-  n2:
-    x: 1000.0
-    y: -7.0
-    a: 0.0
-    width: 5.0
-  p1:
-    x: 0.0
-    y: 7.0
-    a: 180.0
-    width: 5.0
-  p2:
-    x: 1000.0
-    y: 7.0
-    a: 0.0
-    width: 5.0
-time: 20260515-232153
-box_size:
-- 1050.0
-- 28.6
-file_size: 8.82 KB
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/VOA_Si220_1310_L1050_QY_202603/VOA_Si220_1310_L1050_QY_202603_BB.svg b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/VOA_Si220_1310_L1050_QY_202603/VOA_Si220_1310_L1050_QY_202603_BB.svg
deleted file mode 100644
index 3e4e57d..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/primitives/waveguides/VOA_Si220_1310_L1050_QY_202603/VOA_Si220_1310_L1050_QY_202603_BB.svg
+++ /dev/null
@@ -1,30 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="11554.18" height="1336.38" viewBox="-777.09 -668.19 11554.18 1336.38">
-<defs>
-<style type="text/css">
-.l1200d0 {stroke: #F38400; fill: #F38400; fill-opacity: 0.5;}
-.l1205d0 {stroke: #008856; fill: #008856; fill-opacity: 0.5;}
-.l1001t0 {stroke: none; fill: #A1CAF1;}
-</style>
-</defs>
-<rect x="-777.09" y="-668.19" width="11554.18" height="1336.38" fill="white" stroke="none"/>
-<g id="VOA_Si220_1310_L1050_QY_202603" transform="scale(1 -1)">
-<polygon id="0000015554198E50" class="l1200d0" points="-250,-143 10250,-143 10250,143 -250,143"/>
-<polygon id="00000155541982F0" class="l1205d0" points="-248.1,1.9 -251.9,1.9 -251.9,-1.9 -248.1,-1.9"/>
-<polygon id="0000015554198EC0" class="l1205d0" points="-248.1,1.9 -251.9,1.9 -251.9,-1.9 -248.1,-1.9"/>
-<polygon id="0000015554198F30" class="l1205d0" points="10248.1,-1.9 10251.9,-1.9 10251.9,1.9 10248.1,1.9"/>
-<polygon id="000001555419A4A0" class="l1205d0" points="10248.1,-1.9 10251.9,-1.9 10251.9,1.9 10248.1,1.9"/>
-<polygon id="000001555419A820" class="l1205d0" points="25,-45 -25,-45 -25,-95 25,-95"/>
-<polygon id="000001555419A510" class="l1205d0" points="9975,-95 10025,-95 10025,-45 9975,-45"/>
-<polygon id="000001555419AF20" class="l1205d0" points="25,95 -25,95 -25,45 25,45"/>
-<polygon id="000001555419AD60" class="l1205d0" points="9975,45 10025,45 10025,95 9975,95"/>
-<text id="00000155545DD7C0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(-250 0) scale(1 -1)">a1</text>
-<text id="00000155545DD3D0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(-250 0) scale(1 -1)">a0</text>
-<text id="000001555419C9F0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(10250 -0) scale(1 -1)">b1</text>
-<text id="000001555419DFE0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(10250 -0) scale(1 -1)">b0</text>
-<text id="000001555419C690" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(0 -70) scale(1 -1)">n1</text>
-<text id="000001555419D6E0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(10000 -70) scale(1 -1)">n2</text>
-<text id="000001555419DAD0" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(0 70) scale(1 -1)">p1</text>
-<text id="000001555419C570" class="l1001t0" text-anchor="middle" dominant-baseline="central" transform="translate(10000 70) scale(1 -1)">p2</text>
-</g>
-</svg>
\ No newline at end of file
diff --git a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/technology.yml b/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/technology.yml
deleted file mode 100644
index cd77c67..0000000
--- a/mxpic/PDKs/Silterra/EMO1_2ML_CU_Al_RDL/technology.yml
+++ /dev/null
@@ -1,80 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: Technology manifest defining routing types, cross-sections, layer mappings, and default routing settings.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-schema_version: 1.0.0
-foundry: Silterra
-technology: EMO1_2ML_CU_Al_RDL
-source_class: mxpic.foundries.Silterra.EOM1_2ML_CU_RDL
-constants:
-  STD_SMWG_WIDTH: 0.45
-  SLAB_GROWTH: 2
-  W_METAL_MIN: 5
-  SPACING_HEATER_MIN: 2
-  SPACING_METAL_MIN: 4
-  W_HEATER_MIN: 3
-layers:
-  WG_HM: {layer: 275, datatype: 0}
-  WG_STRIP: {layer: 101, datatype: 251}
-  WG_LOWRIB: {layer: 100, datatype: 90}
-  WG_SRIB: {layer: 100, datatype: 90}
-  WG_HIGHRIB: {layer: 232, datatype: 0}
-  HEATER: {layer: 29, datatype: 30}
-  CT_SI: {layer: 268, datatype: 0}
-  CT_GE: {layer: 35, datatype: 0}
-  UTV: {layer: 172, datatype: 0}
-  RDL_VIA: {layer: 194, datatype: 0}
-  UTM: {layer: 173, datatype: 0}
-  UTM2: {layer: 197, datatype: 0}
-  RDL_MET: {layer: 195, datatype: 0}
-  PAD_ELE: {layer: 100, datatype: 170}
-  PAD_OPTICAL: {layer: 100, datatype: 160}
-  PAD_AL: {layer: 145, datatype: 0}
-  WG_N: {layer: 263, datatype: 0}
-  SiN_Rib_WG: {layer: 63, datatype: 30}
-  SSIN0: {layer: 283, datatype: 0}
-  SSIN1: {layer: 289, datatype: 0}
-  SSIN2: {layer: 290, datatype: 0}
-  SSIN3: {layer: 291, datatype: 0}
-routing_types:
-  - euler_bend
-  - standard_bend
-defaults:
-  xsection: strip
-  family: optical
-  width: 0.45
-  radius: 10
-  routing_type: euler_bend
-xsections:
-  strip:
-    family: optical
-    default_width: 0.45
-    default_radius: 10
-    layers:
-      - {layer: WG_HM, growx: 0, growy: 0}
-      - {layer: WG_STRIP, growx: 4, growy: 4}
-  rib_low:
-    family: optical
-    default_width: 0.45
-    default_radius: 10
-    layers:
-      - {layer: WG_HM, growx: 0, growy: 0}
-      - {layer: WG_SRIB, growx: 3, growy: 3}
-      - {layer: WG_STRIP, leftedge: [-0.5, -3], rightedge: [-0.5, -3.5]}
-      - {layer: WG_STRIP, leftedge: [0.5, 3.5], rightedge: [0.5, 3]}
-  metal_1:
-    family: electrical
-    default_width: 5
-    default_radius: 10
-    layers:
-      - {layer: UTM, growx: 0, growy: 0}
-      - {layer: SSIN0, growx: 2.5, growy: 2.5}
-  metal_2:
-    family: electrical
-    default_width: 5
-    default_radius: 10
-    layers:
-      - {layer: UTM2, growx: 0, growy: 0}
-      - {layer: SSIN1, growx: 2.5, growy: 2.5}
diff --git a/mxpic/PDKs/Silterra/directories.yaml b/mxpic/PDKs/Silterra/directories.yaml
deleted file mode 100644
index c3f197a..0000000
--- a/mxpic/PDKs/Silterra/directories.yaml
+++ /dev/null
@@ -1,22 +0,0 @@
-# -----------------------------------------------------------------------------
-# Description: Directory configuration metadata used to locate Silterra PDK library groups and component resources.
-# Inside functions: N/A - declarative YAML metadata/configuration.
-# Developer : Qin Yue @ 2026
-# Organization : OptiHK Limited
-# -----------------------------------------------------------------------------
-level: 4
-root:
-  - PDKs:
-    - primitives:
-      - directional_couplers
-      - edge_couplers
-      - crossings
-      - multimode_interferometers
-      - photodetectors
-    - composites:
-      - MZIs
-    - electronics:
-      - resistors
-      - capacitors
-    - others:
-      - logos
diff --git a/tests/layout-backend-static.test.js b/tests/layout-backend-static.test.js
index 5f08455..a2d1582 100644
--- a/tests/layout-backend-static.test.js
+++ b/tests/layout-backend-static.test.js
@@ -11,14 +11,17 @@ const path = require('path');
 const root = path.resolve(__dirname, '..');
 const backendDir = path.join(root, 'backend');
 const serverPy = fs.readFileSync(path.join(backendDir, 'server.py'), 'utf8');
+const removedInternalPdkPath = ['mxpic', 'PDKs'].join('/');
+const removedEdaPdkRootName = 'EDA_' + 'PDK_ROOT';
+const removedYmlPathName = 'YML_' + 'PATH';
 
 assert(
-  fs.existsSync(path.join(backendDir, 'layout_preview.py')),
-  'backend/layout_preview.py should generate SVG previews from saved layout YAML'
+  !fs.existsSync(path.join(backendDir, 'layout_preview.py')),
+  'EDA backend should not keep the legacy local GDS/SVG preview builder'
 );
 assert(
-  fs.existsSync(path.join(backendDir, 'pdk_registry.py')),
-  'backend/pdk_registry.py should resolve public PDK YAML/GDS assets'
+  !fs.existsSync(path.join(backendDir, 'pdk_registry.py')),
+  'EDA backend should not keep the legacy local PDK GDS registry'
 );
 assert(
   fs.existsSync(path.join(backendDir, 'gds_builder.py')),
@@ -29,12 +32,23 @@ assert(
   'backend/routed_layout_preview.py should create routed SVG previews through mxpic_router'
 );
 assert(
-  serverPy.includes('create_layout_svg_from_gds'),
-  'save-layout route should create a GDS-derived layout SVG preview'
+  fs.existsSync(path.join(backendDir, 'router_dependency.py')),
+  'backend/router_dependency.py should validate build-time mxpic_router runtime dependencies'
 );
 assert(
-  serverPy.includes('create_routed_layout_svg'),
-  'save-layout route should use routed preview generation when links exist'
+  !serverPy.includes('from router_dependency import require_router_stack') &&
+    !serverPy.includes('Verified mxpic_router stack') &&
+    !serverPy.includes('require_router_stack()'),
+  'server startup should not require mxpic_router; only build actions should validate the router stack'
+);
+assert(
+  !serverPy.includes('create_layout_svg_from_gds'),
+  'save-layout route should not use the legacy gdstk-only preview builder'
+);
+assert(
+  serverPy.includes('create_routed_layout_svg') &&
+    !serverPy.includes('if layout_has_links(content):'),
+  'save-layout route should always use routed preview generation through mxpic_router'
 );
 assert(
   serverPy.includes('cell_routes_path') &&
@@ -46,6 +60,13 @@ assert(
   serverPy.includes('svg_url'),
   'save-layout response should include an svg_url for the new layout tab'
 );
+assert(
+  serverPy.includes('RouterStackUnavailable') &&
+    serverPy.includes('except RouterStackUnavailable as e') &&
+    serverPy.includes('"preview_status": preview_status') &&
+    serverPy.includes('"preview_error": preview_error'),
+  'save-layout should still return success and explain skipped SVG preview when mxpic_router is unavailable'
+);
 assert(
   serverPy.includes("@app.route('/api/projects/<project_name>/cells/<cell_name>/layout.svg')"),
   'server should expose a route for saved cell SVG previews'
@@ -63,49 +84,56 @@ assert(
   'backend/technology_manifest.py should read generated technology manifests'
 );
 
-const techManifestPath = path.join(root, 'mxpic', 'PDKs', 'Silterra', 'EMO1_2ML_CU_Al_RDL', 'technology.yml');
 assert(
-  fs.existsSync(techManifestPath),
-  'Silterra technology.yml should be generated into the EDA PDK folder'
-);
-const techManifest = fs.readFileSync(techManifestPath, 'utf8');
-for (const xsection of ['strip', 'rib_low', 'metal_1', 'metal_2']) {
-  assert(techManifest.includes(`${xsection}:`), `technology.yml should include ${xsection}`);
-}
-assert(techManifest.includes('family: optical'), 'technology.yml should classify optical xsections');
-assert(techManifest.includes('family: electrical'), 'technology.yml should classify electrical xsections');
-
-const layoutPreviewPy = fs.readFileSync(path.join(backendDir, 'layout_preview.py'), 'utf8');
-assert(
-  layoutPreviewPy.includes('read_gds') || layoutPreviewPy.includes('load_gds'),
-  'layout_preview.py should load public _BB.gds geometry, not draw only schematic boxes'
+  !serverPy.includes(removedEdaPdkRootName) &&
+    !serverPy.includes(removedYmlPathName) &&
+    !serverPy.includes("'mxpic', 'PDKs'") &&
+    !serverPy.includes(removedInternalPdkPath),
+  'server should not use an internal EDA PDK copy as a separate technology source of truth'
 );
 assert(
-  layoutPreviewPy.includes('_BB.gds') || layoutPreviewPy.includes('gds_path'),
-  'layout_preview.py should resolve public GDS assets for placed components'
+  serverPy.includes('pdks_root = current_pdk_root()') &&
+    serverPy.includes('os.path.exists(os.path.join(technology_path, "technology.yml"))'),
+  'technology list should scan the active role PDK root and only expose folders containing technology.yml'
+);
+assert(
+  serverPy.includes('read_technology_manifest(current_pdk_root()'),
+  'technology manifest API should read technology.yml from the active role PDK root'
+);
+assert(
+  !fs.existsSync(path.join(root, 'mxpic')),
+  'mxpic_EDA should not contain a redundant internal technology copy'
 );
 
 const gdsBuilderPy = fs.readFileSync(path.join(backendDir, 'gds_builder.py'), 'utf8');
 assert(
-  gdsBuilderPy.includes('_cells_have_links') && gdsBuilderPy.includes('Routed Build GDS requires mxpic_router'),
-  'Build GDS should not silently fall back to unrouted gdstk when links are present'
+  gdsBuilderPy.includes('return _build_with_mxpic_router(') &&
+    !gdsBuilderPy.includes('return _build_with_gdstk') &&
+    !gdsBuilderPy.includes('return _build_with_nazca'),
+  'Build GDS should use mxpic_router as the only production builder'
 );
 assert(
-  gdsBuilderPy.includes('_cells_have_elements') &&
-    gdsBuilderPy.includes('Build GDS with Port/Anchor elements requires Nazca') &&
-    gdsBuilderPy.indexOf('if _cells_have_elements(cells):') < gdsBuilderPy.indexOf('return _build_with_gdstk'),
-  'Build GDS should route layouts with Port/Anchor elements through Nazca so element pins survive as cell metadata'
+  gdsBuilderPy.includes('from router_dependency import require_router_stack') &&
+    gdsBuilderPy.includes('require_router_stack()'),
+  'Build GDS API wrapper should validate mxpic_router only when a GDS build is requested'
 );
+
+const routedPreviewPy = fs.readFileSync(path.join(backendDir, 'routed_layout_preview.py'), 'utf8');
 assert(
-    gdsBuilderPy.includes('_build_nazca_element_cells') &&
-    gdsBuilderPy.includes('_build_nazca_element_cell') &&
-    gdsBuilderPy.includes('element.get("pin_number"') &&
-    gdsBuilderPy.includes('_element_pin_names') &&
-    gdsBuilderPy.includes('nd.Pin(pin_name, width=width).put(0.0, y, 180.0)') &&
-    gdsBuilderPy.includes('nd.Pin(anchor_pin_names[index * 2], width=width).put(0.0, y, 180.0)') &&
-    gdsBuilderPy.includes('nd.Pin(anchor_pin_names[index * 2 + 1], width=width).put(0.0, y, 0.0)') &&
-    gdsBuilderPy.includes('element_cell.put(x, y, rotation)'),
-  'Nazca fallback should model Port and Anchor objects as placed element cells with named local nd.Pin definitions'
+  routedPreviewPy.includes('from router_dependency import require_router_stack') &&
+    routedPreviewPy.includes('require_router_stack(require_gdstk=True)'),
+  'Build Layout preview should validate mxpic_router and gdstk only when preview generation is requested'
+);
+
+const routerDependencyPy = fs.readFileSync(path.join(backendDir, 'router_dependency.py'), 'utf8');
+assert(
+  routerDependencyPy.includes('def require_router_stack') &&
+    routerDependencyPy.includes('class RouterStackUnavailable') &&
+    routerDependencyPy.includes('require_gdstk: bool = False') &&
+    routerDependencyPy.includes('importlib.import_module("nazca")') &&
+    routerDependencyPy.includes('mxpic_router.builder') &&
+    routerDependencyPy.includes('_import_mxpic_forge_route'),
+  'router dependency gate should validate mxpic_router, Nazca, optional gdstk, and route backend imports'
 );
 
 const routerDir = path.resolve(root, '..', 'mxpic_router', 'mxpic_router');
@@ -144,3 +172,8 @@ assert(
     serverPy.includes('os.path.relpath(root, path_root)'),
   'library tree leaves should preserve component paths relative to the role PDK root'
 );
+assert(
+  serverPy.includes('f.lower() != "technology.yml"') &&
+    serverPy.includes('component_yml_files'),
+  'component library scanning should ignore technology.yml so it can descend into technology folders'
+);
diff --git a/tests/layout-ui-wiring.test.js b/tests/layout-ui-wiring.test.js
index 42f78a9..1cec144 100644
--- a/tests/layout-ui-wiring.test.js
+++ b/tests/layout-ui-wiring.test.js
@@ -32,6 +32,11 @@ assert(
   canvasHtml.includes('svg_url'),
   'Build Layout should use the backend svg_url response'
 );
+assert(
+  canvasHtml.includes('result.preview_error') &&
+    canvasHtml.includes('Preview skipped: '),
+  'Build Layout should log when the backend saves YAML but skips SVG preview because the router stack is unavailable'
+);
 assert(
   canvasHtml.includes('layoutPreview'),
   'canvas pages should support a layoutPreview tab type'