# =============================================
# mxPIC Cell/Project Definition File
# =============================================
schema_version: "2.0.0"
kind: cell
coordinate_system: gds_y_up
canvas_size:
  width: 500
  height: 500
project: MZM_TX
name: Spliter_1x4
type: composite
version: "1.0.0"

# 1. External Ports (How this cell connects to the outside world)
pins:
- name: Input_io1
  layer: WG_CORE
  element: Input
  pin: io1
  x: 10.0
  y: -110.0
  angle: 180.0
  width: 0.5
- name: OutUp_io1
  layer: WG_CORE
  element: OutUp
  pin: io1
  x: 335.0
  y: -20.0
  angle: 90.0
  width: 0.5
- name: OutUp_io2
  layer: WG_CORE
  element: OutUp
  pin: io2
  x: 325.0
  y: -20.0
  angle: 90.0
  width: 0.5
- name: port_4_io1
  layer: WG_CORE
  element: port_4
  pin: io1
  x: 350.0
  y: -180.0
  angle: 0.0
  width: 0.5

# 2. Instances (The sub-components dropped onto this canvas)
instances:
  MMI_2:
    component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
    x: 90.0
    y: -110.0
    rotation: 0.0
    flip: 0
    flop: 0
    mirror: false
    settings:
    length:

  MMI_3:
    component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
    x: 230.0
    y: -90.0
    rotation: 0.0
    flip: 0
    flop: 0
    mirror: false
    settings:
    length:

elements:
  Input:
    type: port
    x: 10.0
    y: -110.0
    angle: 0.0
    pin_number: 1
    pitch: 10
    layer: WG_CORE
    width: 0.5
    description: ""
    pins:
      - name: Input_io1
        role: io1
  OutUp:
    type: port
    x: 330.0
    y: -20.0
    angle: -90.0
    pin_number: 2
    pitch: 10
    layer: WG_CORE
    width: 0.5
    description: ""
    pins:
      - name: OutUp_io1
        role: io1
      - name: OutUp_io2
        role: io2
  port_4:
    type: port
    x: 350.0
    y: -180.0
    angle: 180.0
    pin_number: 1
    pitch: 10
    layer: WG_CORE
    width: 0.5
    description: ""
    pins:
      - name: port_4_io1
        role: io1
  anchor_1:
    type: anchor
    x: 250.0
    y: -150.0
    angle: 90.0
    pin_number: 1
    pitch: 10
    layer: WG_CORE
    width: 0.5
    description: ""
    pins:
      - name: anchor_1_a1
        role: a1
      - name: anchor_1_b1
        role: b1

# 3. Bundles (Grouped links for multi-bus/parallel routing)
bundles:
  output_bus:
    routing_type: euler_bend
    links:
      - from: MMI_2:a1
        to: Input:Input_io1
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend
      - from: MMI_3:a1
        to: MMI_2:b1
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend
      - from: MMI_3:b1
        to: OutUp:OutUp_io1
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend
      - from: MMI_3:b1
        to: OutUp:OutUp_io2
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend
      - from: MMI_3:b2
        to: OutUp:OutUp_io1
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend
      - from: MMI_2:b2
        to: anchor_1:anchor_1_b1
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend
      - from: anchor_1:anchor_1_a1
        to: port_4:port_4_io1
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend
      - from: anchor_1:anchor_1_a1
        to: anchor_1:anchor_1_b1
        xsection: strip
        family: optical
        width: 0.45
        radius: 10
        routing_type: euler_bend