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Technolgy file archetecture revised with dictionary input method

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2026-06-07 17:07:20 +08:00
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mxpic/technologies/consemi/PSIN_SOI.yml
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schema_version: 1.0.0
foundry: consemi
technology: PSIN_SOI
source:
source_file: Wuyue_SP90_technology_handbook_V0.9.pdf
source_chapter: Chapter 3.2 Drawn Layer
source_pages:
- 11
- 12
notes:
- Layer data was extracted from Table 3-2 of the Wuyue SP90 Technology Handbook V0.9.
constants: {}
layers:
WGS_COR:
layer:
- 11
- 1
description: SOI waveguide shallow etch core
category: drawn
source_table: Table 3-2
WGS_CLD:
layer:
- 11
- 2
description: SOI waveguide shallow etch cladding
category: drawn
source_table: Table 3-2
WGS_TRE:
layer:
- 11
- 3
description: SOI waveguide shallow etch trench
category: drawn
source_table: Table 3-2
WGS_PINREC:
layer:
- 11
- 13
description: SOI waveguide shallow etch pin recognition
category: drawn
source_table: Table 3-2
WGM_COR:
layer:
- 12
- 1
description: SOI waveguide medium etch core
category: drawn
source_table: Table 3-2
WGM_CLD:
layer:
- 12
- 2
description: SOI waveguide medium etch cladding
category: drawn
source_table: Table 3-2
WGM_TRE:
layer:
- 12
- 3
description: SOI waveguide medium etch trench
category: drawn
source_table: Table 3-2
WGM_PINREC:
layer:
- 12
- 13
description: SOI waveguide medium etch pin recognition
category: drawn
source_table: Table 3-2
WGF_COR:
layer:
- 13
- 1
description: SOI waveguide full etch core
category: drawn
source_table: Table 3-2
WGF_CLD:
layer:
- 13
- 2
description: SOI waveguide full etch cladding
category: drawn
source_table: Table 3-2
WGF_DUMB:
layer:
- 13
- 11
description: SOI waveguide full etch dummy block
category: drawn
source_table: Table 3-2
WGF_PINREC:
layer:
- 13
- 13
description: SOI waveguide full etch pin recognition
category: drawn
source_table: Table 3-2
NMOD_DRW:
layer:
- 33
- 9
description: N IMP for medium doped area, such as PD
category: drawn
source_table: Table 3-2
PMOD_DRW:
layer:
- 34
- 9
description: P IMP for medium doped area, such as PD
category: drawn
source_table: Table 3-2
NDD_DRW:
layer:
- 35
- 9
description: N IMP for lightly doped area, such as modulator
category: drawn
source_table: Table 3-2
PDD_DRW:
layer:
- 36
- 9
description: P IMP for lightly doped area, such as modulator
category: drawn
source_table: Table 3-2
NCT_DRW:
layer:
- 37
- 9
description: N+ IMP for heavily doped area, such as contact via
category: drawn
source_table: Table 3-2
PCT_DRW:
layer:
- 38
- 9
description: P+ IMP for heavily doped area, such as contact via
category: drawn
source_table: Table 3-2
SNS_COR:
layer:
- 21
- 1
description: SiN waveguide shallow etch core
category: drawn
source_table: Table 3-2
SNS_CLD:
layer:
- 21
- 2
description: SiN waveguide shallow etch cladding
category: drawn
source_table: Table 3-2
SNS_TRE:
layer:
- 21
- 3
description: SiN waveguide shallow etch trench
category: drawn
source_table: Table 3-2
SNS_PINREC:
layer:
- 21
- 13
description: SiN waveguide shallow etch pin recognition
category: drawn
source_table: Table 3-2
SNF_COR:
layer:
- 22
- 1
description: SiN waveguide full etch core
category: drawn
source_table: Table 3-2
SNF_CLD:
layer:
- 22
- 2
description: SiN waveguide full etch cladding
category: drawn
source_table: Table 3-2
SNF_DUMB:
layer:
- 22
- 11
description: SiN waveguide full etch dummy block
category: drawn
source_table: Table 3-2
SNF_PINREC:
layer:
- 22
- 13
description: SiN waveguide full etch pin recognition
category: drawn
source_table: Table 3-2
GE_DRW:
layer:
- 50
- 9
description: Ge trench
category: drawn
source_table: Table 3-2
GE_DUMB:
layer:
- 50
- 11
description: Ge trench dummy block
category: drawn
source_table: Table 3-2
SAB_REV:
layer:
- 51
- 8
description: Salicide area for contact via
category: drawn
source_table: Table 3-2
CT_DRW:
layer:
- 60
- 9
description: Contact via
category: drawn
source_table: Table 3-2
M1_DRW:
layer:
- 71
- 9
description: Metal 1
category: drawn
source_table: Table 3-2
M1_SLOT:
layer:
- 71
- 5
description: Metal 1 slot
category: drawn
source_table: Table 3-2
M1_DUMB:
layer:
- 71
- 11
description: Metal 1 dummy block
category: drawn
source_table: Table 3-2
M1_PINREC:
layer:
- 71
- 13
description: Metal 1 pin recognition
category: drawn
source_table: Table 3-2
MTH_DRW:
layer:
- 80
- 9
description: TiN Heater
category: drawn
source_table: Table 3-2
EC1_DRW:
layer:
- 90
- 9
description: Nitride for edge coupler between M1 and M2
category: drawn
source_table: Table 3-2
V1_DRW:
layer:
- 61
- 9
description: Via 1
category: drawn
source_table: Table 3-2
M2_DRW:
layer:
- 72
- 9
description: Metal 2
category: drawn
source_table: Table 3-2
M2_SLOT:
layer:
- 72
- 5
description: Metal 2 slot
category: drawn
source_table: Table 3-2
M2_DUMB:
layer:
- 72
- 11
description: Metal 2 dummy block
category: drawn
source_table: Table 3-2
M2_PINREC:
layer:
- 72
- 13
description: Metal 2 pin recognition
category: drawn
source_table: Table 3-2
EC2_DRW:
layer:
- 91
- 9
description: Nitride for edge coupler between M2 and M3
category: drawn
source_table: Table 3-2
V2_DRW:
layer:
- 62
- 9
description: Via 2
category: drawn
source_table: Table 3-2
M3_DRW:
layer:
- 73
- 9
description: Metal 3
category: drawn
source_table: Table 3-2
M3_SLOT:
layer:
- 73
- 5
description: Metal 3 slot
category: drawn
source_table: Table 3-2
M3_DUMB:
layer:
- 73
- 11
description: Metal 3 dummy block
category: drawn
source_table: Table 3-2
M3_PINREC:
layer:
- 73
- 13
description: Metal 3 pin recognition
category: drawn
source_table: Table 3-2
EC3_DRW:
layer:
- 92
- 9
description: Nitride for edge coupler between M3 and TM
category: drawn
source_table: Table 3-2
TV_DRW:
layer:
- 63
- 9
description: Top Via
category: drawn
source_table: Table 3-2
TM_DRW:
layer:
- 74
- 9
description: Top metal
category: drawn
source_table: Table 3-2
TM_SLOT:
layer:
- 74
- 5
description: Top metal slot
category: drawn
source_table: Table 3-2
TM_DUMB:
layer:
- 74
- 11
description: Top metal dummy block
category: drawn
source_table: Table 3-2
TM_PINREC:
layer:
- 74
- 13
description: Top metal pin recognition
category: drawn
source_table: Table 3-2
PA_DRW:
layer:
- 100
- 9
description: Metal pad open for testing and packaging
category: drawn
source_table: Table 3-2
DO1_DRW:
layer:
- 101
- 9
description: SiN open for optical coupling
category: drawn
source_table: Table 3-2
DT_DRW:
layer:
- 110
- 9
description: Deep Si Trench for edge coupler
category: drawn
source_table: Table 3-2
LOGO_DRW:
layer:
- 226
- 9
description: Logo, all logos print on wafer must only use this layer
category: drawn
source_table: Table 3-2
METAL_DUMB:
layer:
- 227
- 11
description: Metal dummy block
category: drawn
source_table: Table 3-2
ALL_DUMB:
layer:
- 228
- 11
description: all layer dummy block
category: drawn
source_table: Table 3-2
REC_TXT:
layer:
- 229
- 12
description: Text layer, not print on wafer, use for description such as polarization
and optical band description
category: drawn
source_table: Table 3-2
REC_MARK:
layer:
- 229
- 15
description: Mark layer, not print on wafer
category: drawn
source_table: Table 3-2
OIOGC_PORT:
layer:
- 230
- 14
description: GC optical port, for wafer-level testing recognition
category: drawn
source_table: Table 3-2
OIOGC_TXT:
layer:
- 230
- 12
description: GC optical port recognition text, not print on wafer
category: drawn
source_table: Table 3-2
OIOEC_PORT:
layer:
- 231
- 14
description: EC optical port, for wafer-level testing recognition
category: drawn
source_table: Table 3-2
OIOEC_TXT:
layer:
- 231
- 12
description: EC optical port recognition text, not print on wafer
category: drawn
source_table: Table 3-2
EIORF_PORT:
layer:
- 232
- 14
description: RF electrical port, for wafer-level testing recognition
category: drawn
source_table: Table 3-2
EIORF_TXT:
layer:
- 232
- 12
description: RF electrical port recognition text, not print on wafer
category: drawn
source_table: Table 3-2
EIODC_PORT:
layer:
- 233
- 14
description: DC electrical port, for wafer-level testing recognition
category: drawn
source_table: Table 3-2
EIODC_TXT:
layer:
- 233
- 12
description: DC electrical port recognition text, not print on wafer
category: drawn
source_table: Table 3-2
OPTSI_TXT:
layer:
- 240
- 12
description: Pin rectangle text, for Si routing pin recognition
category: drawn
source_table: Table 3-2
OPTSIN_TXT:
layer:
- 241
- 12
description: Pin rectangle text, for SiN routing pin recognition
category: drawn
source_table: Table 3-2
EPTM_TXT:
layer:
- 246
- 12
description: Pin rectangle text, for all metal layer routing pin recognition
category: drawn
source_table: Table 3-2
DEV_AREA:
layer:
- 251
- 16
description: Device drawn area marking layer, indicates the boundary
category: drawn
source_table: Table 3-2
BB_AREA:
layer:
- 260
- 16
description: Blackbox area
category: drawn
source_table: Table 3-2
BB_TXT:
layer:
- 260
- 12
description: Blackbox label text, not print on wafer
category: drawn
source_table: Table 3-2
EC_AREA:
layer:
- 261
- 16
description: Device area marking layer for non-Blackbox EC. All the EC1/2/3 layer
must be covered by the EC_AREA layer.
category: drawn
source_table: Table 3-2
BBSI_AREA:
layer:
- 265
- 16
description: Blackbox area marking layer for Si device
category: drawn
source_table: Table 3-2
BBSIN_AREA:
layer:
- 266
- 16
description: Blackbox area marking layer for SiN device
category: drawn
source_table: Table 3-2
BBEC_AREA:
layer:
- 267
- 16
description: Blackbox area marking layer for EC device
category: drawn
source_table: Table 3-2
BBACT_AREA:
layer:
- 268
- 16
description: Blackbox area marking layer for GC device and active device using
metal layers
category: drawn
source_table: Table 3-2
FORBID_AREA:
layer:
- 290
- 16
description: Forbidden area for any drawing pattern
category: drawn
source_table: Table 3-2
xsections: {}
materials: {}