From 531c1f1f452fc982b274623835b24fea47add0d3 Mon Sep 17 00:00:00 2001 From: pengkun0129 Date: Thu, 4 Jun 2026 17:56:28 +0000 Subject: [PATCH] =?UTF-8?q?=E4=B8=8A=E4=BC=A0=E6=96=87=E4=BB=B6=E8=87=B3?= =?UTF-8?q?=E3=80=8C/=E3=80=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- WORK_LOG.md | 50 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/WORK_LOG.md b/WORK_LOG.md index b384583..e9569bd 100644 --- a/WORK_LOG.md +++ b/WORK_LOG.md @@ -40,10 +40,6 @@ The routing method selection logic was updated so perpendicular port-angle cases mxpic_router/mxpic_router/builder.py mxpic_router/tests/test_eda_router_contract.py - - - - ## 2026-06-04 ### Scope @@ -93,3 +89,49 @@ Contract tests were added and updated to cover automatic S-bend `Lstart` assignm mxpic_router/mxpic_router/builder.py mxpic_router/tests/test_eda_router_contract.py + +## 2026-06-05 + +### Scope + +Backend S-bend grouping contract and `Lstart` ordering refinement in `mxpic_router`. + +### Summary + +Recent work focused on improving automatic S-bend spacing behavior for multi-port routing cases, especially MMI-to-port and resistor-array routing patterns. + +### Completed Work + +#### 1. Explicit Route Group Metadata Support + +Backend support was added for explicit link grouping metadata from the layout YAML. + +`LinkSpec` now records the parent bundle name and accepts optional route grouping fields such as `route_group`, `routeGroup`, `group`, `bundle_group`, and `bundleGroup`. + +This prepares the backend for future frontend-provided bundle/group selection while preserving the existing geometry-based fallback behavior. + +#### 2. S-Bend Stage Grouping Refinement + +The S-bend grouping key was refined to avoid mixing routes from different routing stages within the same YAML bundle. + +Automatic S-bend routes are now grouped by routing axis, direction, route stage/span, xsection, width, and radius unless an explicit route group is provided. + +This prevents separate stages such as component-to-component routes and component-to-port routes from interfering with each other's `Lstart` ordering. + +#### 3. Lstart Ordering Correction + +The `Lstart` ordering logic was reviewed for resistor-array and MMI-to-port routing cases. + +The sorting basis was corrected to use the source-side route coordinate for same-direction fan-out/fan-in routes, and S-bend axis detection was updated to prefer port direction over raw geometric span. + +This fixes cases where routes with large vertical offset were incorrectly classified and assigned reversed `Lstart` values. + +#### 4. Test Coverage Update + +Contract tests were added and updated to cover explicit route group metadata parsing, route-stage separation, MMI-to-port two-output fan-out ordering, width-aware `Lstart` spacing, and preservation of earlier S-bend spacing behavior. + +### Modified Files + +mxpic_router/mxpic_router/eda_loader.py +mxpic_router/mxpic_router/builder.py +mxpic_router/tests/test_eda_router_contract.py