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Reviewed-on: #4
mxpic_EDA
The EDA coding for the layout for optihk
requirements
flask
Frontend - backend GDS bridge
Each canvas in the fronend should create a same name .yaml file. This .yaml should contain the following parts.
- basic description : name, type, version
- ports : the output connection ports for this canvas object
- instances : the instance objects from PDK or other canvas, together with their x, y, a, mirror informations.
- bundles : 1-1 or N-N conenctions that used for auto routing. "This" refers to the canvas ports.
[ Project Canvas ]
│ (Contains instances of Component A and Component B)
▼
[ Component A Canvas ]
│ (Contains instances of DC_2x2 and Ubend)
▼
[ PDK Primitives ] ──> (Loads raw .gds + physical port data .yml)
# ==========================================
# mxPIC Cell/Project Definition File
# ==========================================
name: MMI_Splitter_Module # Name of this cell/component/project
type: composite # "primitive" (PDK base) or "composite" (hierarchical)
version: "1.0.0"
# 1. External Ports (How this cell connects to the outside world)
ports:
- name: in0
layer: WG_CORE
x: 0.0
y: 0.0
angle: 180.0
width: 0.5
- name: out0
layer: WG_CORE
x: 100.0
y: 10.0
angle: 0.0
width: 0.5
- name: out1
layer: WG_CORE
x: 100.0
y: -10.0
angle: 0.0
width: 0.5
# 2. Instances (The sub-components dropped onto this canvas)
instances:
mmi_inst1:
component: MMI_2x2 # References another PDK cell or composite YAML
x: 20.0 # Placement origin X
y: 0.0 # Placement origin Y
rotation: 0.0 # Rotation angle in degrees
mirror: false # True/False for layout mirroring
settings: # Local parameter overrides if parametric
length: 25.5
ubend_top:
component: Ubend
x: 60.0
y: 5.0
rotation: 0.0
mirror: false
ubend_bottom:
component: Ubend
x: 60.0
y: -5.0
rotation: 0.0
mirror: true # Flipped for symmetrical routing
# 3. Bundles (Grouped links for multi-bus/parallel routing)
bundles:
output_bus:
routing_type: euler_bend # Metadata for the backend router
links:
- from: ubend_top:out0
to: this:out0
- from: ubend_bottom:out0
to: this:out1
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