Routing problem for multi-pin port and anchors are debugged
This commit is contained in:
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+1
-1
@@ -1,4 +1,4 @@
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{
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"name": "mxpic_project_1",
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"name": "MZM_TX",
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"technology": "Silterra/EMO1_2ML_CU_Al_RDL"
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}
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After Width: | Height: | Size: 465 KiB |
@@ -0,0 +1,102 @@
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# =============================================
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# mxPIC Cell/Project Definition File
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# =============================================
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schema_version: "2.0.0"
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kind: cell
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coordinate_system: gds_y_up
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||||
canvas_size:
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width: 5000
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height: 5000
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project: MZM_TX
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name: MZM_TX
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type: project
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version: "1.0.0"
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# 1. External Ports (How this cell connects to the outside world)
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pins: []
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# 2. Instances (The sub-components dropped onto this canvas)
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instances:
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Spliter_1x4:
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component: Spliter_1x4
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x: 330.0
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y: -630.0
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rotation: 0.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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MZM_1:
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component: Silterra/EMO1_2ML_CU_Al_RDL/composites/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603
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x: 750.0
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y: -460.0
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rotation: 0.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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EC_1:
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component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604
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x: 0.0
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y: -920.0
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rotation: 180.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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elements:
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anchor_2:
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type: anchor
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x: 470.0
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y: -840.0
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angle: 0.0
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pin_number: 1
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: anchor_2_a1
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role: a1
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- name: anchor_2_b1
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role: b1
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# 3. Bundles (Grouped links for multi-bus/parallel routing)
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bundles:
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output_bus:
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routing_type: euler_bend
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links:
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- from: MZM_1:a1
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to: Spliter_1x4:OutUp_io2
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: Spliter_1x4:OutUp_io1
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to: MZM_1:a2
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: anchor_2:anchor_2_b1
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to: EC_1:a1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: anchor_2:anchor_2_a1
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to: Spliter_1x4:Input_io1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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+152
-106
File diff suppressed because one or more lines are too long
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Before Width: | Height: | Size: 149 KiB After Width: | Height: | Size: 179 KiB |
@@ -0,0 +1,192 @@
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# =============================================
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# mxPIC Cell/Project Definition File
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# =============================================
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schema_version: "2.0.0"
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kind: cell
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coordinate_system: gds_y_up
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canvas_size:
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width: 500
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height: 500
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project: MZM_TX
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name: Spliter_1x4
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type: composite
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version: "1.0.0"
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# 1. External Ports (How this cell connects to the outside world)
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pins:
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- name: Input_io1
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layer: WG_CORE
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element: Input
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pin: io1
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x: 10.0
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y: -110.0
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angle: 180.0
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width: 0.5
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- name: OutUp_io1
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layer: WG_CORE
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element: OutUp
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pin: io1
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x: 335.0
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y: -20.0
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angle: 90.0
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width: 0.5
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- name: OutUp_io2
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layer: WG_CORE
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element: OutUp
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pin: io2
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x: 325.0
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y: -20.0
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angle: 90.0
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width: 0.5
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- name: port_4_io1
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layer: WG_CORE
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element: port_4
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pin: io1
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x: 350.0
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y: -180.0
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angle: 0.0
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width: 0.5
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# 2. Instances (The sub-components dropped onto this canvas)
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instances:
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MMI_2:
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component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
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x: 90.0
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y: -110.0
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rotation: 0.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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MMI_3:
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component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
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x: 230.0
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y: -90.0
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rotation: 0.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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elements:
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Input:
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type: port
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x: 10.0
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y: -110.0
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angle: 0.0
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pin_number: 1
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: Input_io1
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role: io1
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OutUp:
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type: port
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x: 330.0
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y: -20.0
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angle: -90.0
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pin_number: 2
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: OutUp_io1
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role: io1
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- name: OutUp_io2
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role: io2
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port_4:
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type: port
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x: 350.0
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y: -180.0
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angle: 180.0
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pin_number: 1
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: port_4_io1
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role: io1
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anchor_1:
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type: anchor
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x: 250.0
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y: -150.0
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angle: 90.0
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pin_number: 1
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: anchor_1_a1
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role: a1
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- name: anchor_1_b1
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role: b1
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# 3. Bundles (Grouped links for multi-bus/parallel routing)
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bundles:
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output_bus:
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routing_type: euler_bend
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links:
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- from: MMI_2:a1
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to: Input:Input_io1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_3:a1
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to: MMI_2:b1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_3:b1
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to: OutUp:OutUp_io1
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xsection: strip
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||||
family: optical
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width: 0.45
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||||
radius: 10
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||||
routing_type: euler_bend
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- from: MMI_3:b1
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to: OutUp:OutUp_io2
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xsection: strip
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||||
family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_3:b2
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to: OutUp:OutUp_io1
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xsection: strip
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||||
family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_2:b2
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to: anchor_1:anchor_1_b1
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xsection: strip
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||||
family: optical
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||||
width: 0.45
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||||
radius: 10
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||||
routing_type: euler_bend
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||||
- from: anchor_1:anchor_1_a1
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to: port_4:port_4_io1
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||||
xsection: strip
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||||
family: optical
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||||
width: 0.45
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||||
radius: 10
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||||
routing_type: euler_bend
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||||
- from: anchor_1:anchor_1_a1
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||||
to: anchor_1:anchor_1_b1
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||||
xsection: strip
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||||
family: optical
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||||
width: 0.45
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||||
radius: 10
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||||
routing_type: euler_bend
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||||
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 78 KiB |
@@ -1,117 +0,0 @@
|
||||
# =============================================
|
||||
# mxPIC Cell/Project Definition File
|
||||
# =============================================
|
||||
schema_version: "2.0.0"
|
||||
kind: cell
|
||||
coordinate_system: gds_y_up
|
||||
canvas_size:
|
||||
width: 5000
|
||||
height: 500
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||||
project: mxpic_project_1
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||||
name: canvas_1
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||||
type: composite
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||||
version: "1.0.0"
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||||
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||||
# 1. External Ports (How this cell connects to the outside world)
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||||
ports:
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||||
- name: port
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||||
layer: WG_CORE
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||||
x: 103.5
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y: -127.3
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||||
angle: 180.0
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||||
width: 0.5
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||||
- name: port_1
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||||
layer: WG_CORE
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||||
x: 108.7
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||||
y: -252.6
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||||
angle: 180.0
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width: 0.5
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||||
- name: port_2
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||||
layer: WG_CORE
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||||
x: 497.4
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||||
y: -131.6
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angle: 0.0
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||||
width: 0.5
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||||
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# 2. Instances (The sub-components dropped onto this canvas)
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instances:
|
||||
MMI_1:
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||||
component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
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||||
x: 177.9
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||||
y: -252.1
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||||
rotation: 0.0
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||||
flip: 0
|
||||
flop: 0
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||||
mirror: false
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||||
settings:
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||||
length:
|
||||
|
||||
MMI_2:
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||||
component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
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||||
x: 356.7
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||||
y: -142.9
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||||
rotation: 0.0
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||||
flip: 0
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||||
flop: 0
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||||
mirror: false
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||||
settings:
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||||
length:
|
||||
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||||
elements:
|
||||
port:
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||||
type: port
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||||
x: 103.5
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||||
y: -127.3
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||||
angle: 0.0
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||||
port_number: 1
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||||
pitch: 10
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||||
layer: WG_CORE
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||||
width: 0.5
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||||
description: ""
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port_1:
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type: port
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||||
x: 108.7
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y: -252.6
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||||
angle: 0.0
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||||
port_number: 1
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pitch: 10
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||||
layer: WG_CORE
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width: 0.5
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||||
description: ""
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||||
port_2:
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type: port
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||||
x: 497.4
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||||
y: -131.6
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||||
angle: 180.0
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port_number: 1
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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||||
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# 3. Bundles (Grouped links for multi-bus/parallel routing)
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||||
bundles:
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||||
output_bus:
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||||
routing_type: euler_bend
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||||
links:
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||||
- from: MMI_1:a1
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||||
to: port_1:port
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||||
xsection: strip
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||||
family: optical
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||||
width: 0.45
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||||
radius: 10
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||||
routing_type: euler_bend
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||||
- from: MMI_1:b1
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||||
to: MMI_2:a1
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||||
xsection: strip
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||||
family: optical
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||||
width: 0.45
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||||
radius: 10
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||||
routing_type: euler_bend
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||||
- from: MMI_2:b1
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||||
to: port_2:port
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||||
xsection: strip
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||||
family: optical
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||||
width: 0.45
|
||||
radius: 10
|
||||
routing_type: euler_bend
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||||
File diff suppressed because one or more lines are too long
|
Before Width: | Height: | Size: 195 KiB |
@@ -1,71 +0,0 @@
|
||||
# =============================================
|
||||
# mxPIC Cell/Project Definition File
|
||||
# =============================================
|
||||
schema_version: "2.0.0"
|
||||
kind: cell
|
||||
coordinate_system: gds_y_up
|
||||
canvas_size:
|
||||
width: 5000
|
||||
height: 5000
|
||||
project: mxpic_project_1
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||||
name: mxpic_project_1
|
||||
type: project
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||||
version: "1.0.0"
|
||||
|
||||
# 1. External Ports (How this cell connects to the outside world)
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||||
ports:
|
||||
- name: port
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||||
layer: WG_CORE
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||||
x: 50.0
|
||||
y: -150.0
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||||
angle: 0.0
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||||
width: 0.5
|
||||
|
||||
# 2. Instances (The sub-components dropped onto this canvas)
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||||
instances:
|
||||
canvas_1:
|
||||
component: canvas_1
|
||||
x: 476.9
|
||||
y: -1056.4
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||||
rotation: 0.0
|
||||
flip: 0
|
||||
flop: 0
|
||||
mirror: false
|
||||
settings:
|
||||
length:
|
||||
|
||||
canvas_1_1:
|
||||
component: canvas_1
|
||||
x: 1139.8
|
||||
y: -958.5
|
||||
rotation: 0.0
|
||||
flip: 0
|
||||
flop: 0
|
||||
mirror: false
|
||||
settings:
|
||||
length:
|
||||
|
||||
elements:
|
||||
port:
|
||||
type: port
|
||||
x: 50.0
|
||||
y: -150.0
|
||||
angle: 180.0
|
||||
port_number: 1
|
||||
pitch: 10
|
||||
layer: WG_CORE
|
||||
width: 0.5
|
||||
description: ""
|
||||
|
||||
# 3. Bundles (Grouped links for multi-bus/parallel routing)
|
||||
bundles:
|
||||
output_bus:
|
||||
routing_type: euler_bend
|
||||
links:
|
||||
- from: canvas_1_1:port_1
|
||||
to: canvas_1:port_2
|
||||
xsection: strip
|
||||
family: optical
|
||||
width: 0.45
|
||||
radius: 10
|
||||
routing_type: euler_bend
|
||||
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