=
211 lines
4.0 KiB
YAML
211 lines
4.0 KiB
YAML
# =============================================
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# mxPIC Cell/Project Definition File
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# =============================================
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schema_version: "2.0.0"
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kind: cell
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coordinate_system: gds_y_up
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canvas_size:
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width: 500
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height: 600
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project: mxpic_project_1
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name: canvas_1
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type: composite
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version: "1.0.0"
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# 1. External Ports (How this cell connects to the outside world)
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pins:
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- name: port_io1
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layer: WG_CORE
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element: port
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pin: io1
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x: 40.0
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y: -90.0
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angle: 180.0
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width: 0.5
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- name: port_1_io1
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layer: WG_CORE
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element: port_1
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pin: io1
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x: 410.0
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y: -35.0
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angle: 0.0
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width: 0.5
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- name: port_1_io2
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layer: WG_CORE
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element: port_1
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pin: io2
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x: 410.0
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y: -25.0
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angle: 0.0
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width: 0.5
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- name: port_2_io1
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layer: WG_CORE
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element: port_2
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pin: io1
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x: 390.0
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y: -215.0
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angle: 0.0
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width: 0.5
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- name: port_2_io2
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layer: WG_CORE
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element: port_2
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pin: io2
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x: 390.0
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y: -205.0
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angle: 0.0
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width: 0.5
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# 2. Instances (The sub-components dropped onto this canvas)
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instances:
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MMI_1:
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component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
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x: 130.0
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y: -90.0
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rotation: 0.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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MMI_2:
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component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
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x: 280.0
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y: -30.0
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rotation: 0.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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MMI_3:
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component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
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x: 320.1
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y: -144.7
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rotation: 0.0
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flip: 0
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flop: 0
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mirror: false
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settings:
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length:
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elements:
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port:
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type: port
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x: 40.0
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y: -90.0
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angle: 180.0
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pin_number: 1
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: port_io1
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role: io1
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port:
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type: port
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x: 40.0
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y: -90.0
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angle: 0.0
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pin_number: 1
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: port_io1
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role: io1
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port_1:
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type: port
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x: 410.0
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y: -30.0
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angle: 180.0
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pin_number: 2
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: port_1_io1
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role: io1
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- name: port_1_io2
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role: io2
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port_2:
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type: port
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x: 390.0
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y: -210.0
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angle: 180.0
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pin_number: 2
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pitch: 10
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layer: WG_CORE
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width: 0.5
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description: ""
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pins:
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- name: port_2_io1
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role: io1
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- name: port_2_io2
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role: io2
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# 3. Bundles (Grouped links for multi-bus/parallel routing)
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bundles:
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output_bus:
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routing_type: euler_bend
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links:
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- from: MMI_1:a1
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to: port:port_io1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_2:a1
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to: MMI_1:b1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_3:a1
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to: MMI_1:b2
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_2:b1
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to: port_1:port_1_io1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_2:b1
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to: port_1:port_1_io2
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_2:b2
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to: port_1:port_1_io1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_3:b1
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to: port_2:port_2_io2
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend
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- from: MMI_3:b2
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to: port_2:port_2_io1
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xsection: strip
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family: optical
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width: 0.45
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radius: 10
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routing_type: euler_bend |