210 lines
9.1 KiB
Markdown
210 lines
9.1 KiB
Markdown
# Backend Routing Work Log - PENG KUN
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## 2026-06-02
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### Scope
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Backend routing generation and GDS build consistency in `mxpic_router`.
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### Summary
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Recent work focused on improving routing correctness in `mxpic_router/mxpic_router/builder.py`, including route width investigation, rotation convention alignment, and perpendicular routing behavior correction.
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### Completed Work
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#### 1. Route Width Issue Investigation
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A mismatch was identified between the route width configured in the EDA frontend and the width exported into the layout YAML/GDS build flow.
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Backend tracing showed that the router consumed the width value from the YAML as expected, while the exported YAML still used the default width in several cases. The issue was isolated to the frontend serialization/export logic and reported to the frontend owner for correction.
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#### 2. Frontend/Backend Rotation Convention Alignment
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A rotation inconsistency was identified between the EDA canvas representation and the generated GDS layout.
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For rotated devices such as resistors, the frontend display and backend placement used different rotation conventions, which caused incorrect component orientation or port direction in the final GDS.
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The backend build logic was updated to convert EDA instance rotation into layout rotation during component placement and metadata pin registration, while preserving the original behavior for element-based ports and anchors.
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#### 3. Perpendicular Routing Behavior Correction
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A routing issue was identified for port pairs with a 90-degree or 270-degree angle difference.
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The previous automatic route selection fell back to the generic `bend_p2p` method, which could generate a `bend - diagonal straight - bend` path.
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The routing method selection logic was updated so perpendicular port-angle cases use `strt_bend_strt_p2p`, producing the expected `straight - bend - straight` routing style.
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### Modified Files
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mxpic_router/mxpic_router/builder.py
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mxpic_router/tests/test_eda_router_contract.py
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## 2026-06-04
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### Scope
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Backend routing spacing behavior and automatic S-bend refinement in `mxpic_router`.
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### Summary
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Recent work focused on reducing overlap and crossing risks for grouped automatic S-bend connections while keeping the generated GDS impact limited.
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### Completed Work
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#### 1. S-Bend Spacing Issue Investigation
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A route overlap issue was investigated for layouts containing multiple parallel or near-parallel automatic S-bend routes.
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The issue was most visible when several component output ports were connected to several port elements. In these cases, the initial straight section of multiple S-bends could overlap or become too close when source and target ports were arranged in parallel.
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#### 2. Conservative `Lstart`-Based S-Bend Adjustment
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Spacing control was implemented through the native Nazca `sbend_p2p` `Lstart` parameter.
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The backend now groups compatible automatic S-bend routes and assigns different `Lstart` values before route generation. This preserves the native S-bend route style and avoids manually constructed detours.
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The adjustment applies only to automatic `sbend_p2p` routes. Manual-point routes, U-bends, perpendicular `strt_bend_strt_p2p` routes, and generic bend routes are left unchanged.
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#### 3. Bundle-Level Route Grouping and Ordering
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Compatible S-bend routes are grouped by routing direction, xsection, width, and radius. The `Lstart` assignment logic was refined for both same-direction fan-out/fan-in routes and symmetric convergence/divergence routes, so outer routes can receive larger offsets when needed.
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#### 4. Width-Aware Spacing Step
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The base step is now calculated as:
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```text
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route width + 10um
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```
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For example, a 0.5um-wide route uses a 10.5um `Lstart` step, while a 40um-wide route uses a 50um `Lstart` step.
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#### 5. Test Coverage Update
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Contract tests were added and updated to cover automatic S-bend `Lstart` assignment, bundle-level grouping behavior, route ordering, width-aware spacing, and preservation of earlier rotation and perpendicular-routing fixes.
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### Modified Files
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mxpic_router/mxpic_router/builder.py
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mxpic_router/tests/test_eda_router_contract.py
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## 2026-06-05
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### Scope
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Backend S-bend grouping contract and `Lstart` ordering refinement in `mxpic_router`.
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### Summary
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Recent work focused on improving automatic S-bend spacing behavior for multi-port routing cases, especially MMI-to-port and resistor-array routing patterns.
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### Completed Work
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#### 1. Explicit Route Group Metadata Support
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Backend support was added for explicit link grouping metadata from the layout YAML.
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`LinkSpec` now records the parent bundle name and accepts optional route grouping fields such as `route_group`, `routeGroup`, `group`, `bundle_group`, and `bundleGroup`.
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This prepares the backend for future frontend-provided bundle/group selection while preserving the existing geometry-based fallback behavior.
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#### 2. S-Bend Stage Grouping Refinement
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The S-bend grouping key was refined to avoid mixing routes from different routing stages within the same YAML bundle.
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Automatic S-bend routes are now grouped by routing axis, direction, route stage/span, xsection, width, and radius unless an explicit route group is provided.
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This prevents separate stages such as component-to-component routes and component-to-port routes from interfering with each other's `Lstart` ordering.
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#### 3. Lstart Ordering Correction
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The `Lstart` ordering logic was reviewed for resistor-array and MMI-to-port routing cases.
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The sorting basis was corrected to use the source-side route coordinate for same-direction fan-out/fan-in routes, and S-bend axis detection was updated to prefer port direction over raw geometric span.
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This fixes cases where routes with large vertical offset were incorrectly classified and assigned reversed `Lstart` values.
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#### 4. Test Coverage Update
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Contract tests were added and updated to cover explicit route group metadata parsing, route-stage separation, MMI-to-port two-output fan-out ordering, width-aware `Lstart` spacing, and preservation of earlier S-bend spacing behavior.
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### Modified Files
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mxpic_router/mxpic_router/eda_loader.py
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mxpic_router/mxpic_router/builder.py
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mxpic_router/tests/test_eda_router_contract.py
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## 2026-06-09
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### Scope
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Frontend/backend routing metadata integration and electrical routing behavior review.
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### Summary
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Recent work focused on aligning the backend route grouping logic with the updated EDA frontend bundle-group export format, and reviewing why resistor routes were not using PCB-style routing.
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### Completed Work
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#### 1. Frontend Bundle Group Integration
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The updated frontend exports user-selected route bundle groups as YAML bundle keys instead of duplicating `bundle_group` inside each link.
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The backend route grouping logic was updated to treat custom YAML bundle keys as explicit route groups for S-bend `Lstart` spacing.
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Default groups such as `output_bus`, `free_wires`, and `free_wires_*` are still treated as fallback groups to avoid unintentionally merging unrelated free-wire routes.
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#### 2. Contract Test Update
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A contract test was added to verify that custom frontend bundle keys are recognized as backend route groups, while default bundle names remain excluded from explicit grouping.
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#### 3. PCB Routing Condition Review
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The PCB routing condition was reviewed for resistor-based test layouts.
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The backend currently enables `PCB=True` based on route `xsection` only. Routes using `metal_1`, `metal1`, `metal_2`, or `metal2` enable PCB routing; routes exported as `strip` remain optical-style routes.
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The current resistor test YAML was found to export `xsection: strip` and `family: optical`, so the issue was traced to frontend route metadata export rather than the backend PCB flag logic.
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### Modified Files
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mxpic_router/mxpic_router/builder.py
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mxpic_router/tests/test_eda_router_contract.py
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## 2026-06-10
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### Scope
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Backend routing condition alignment and automatic route direction normalization in `mxpic_router`.
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### Summary
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Recent work focused on aligning backend routing behavior with updated frontend metadata and reducing direction-related crossing issues in bundled automatic routes.
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### Completed Work
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#### 1. PCB Routing Condition Update
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The PCB routing condition was updated to use the YAML link `family` field instead of route `xsection`.
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Routes with `family: electrical` now enable `PCB=True`, regardless of the specific metal layer or xsection name. Optical routes remain unchanged.
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#### 2. Automatic Route Direction Normalization
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Automatic bundled routes are now normalized to route from the lower-x endpoint to the higher-x endpoint.
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This keeps route direction consistent inside the same bundle and reduces crossing risks caused by mixed left-to-right and right-to-left link definitions.
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#### 3. Test Coverage Update
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Contract tests were added to verify electrical-family PCB routing and left-to-right automatic route ordering.
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### Modified Files
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mxpic_router/mxpic_router/builder.py
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mxpic_router/tests/test_eda_router_contract.py
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