PotatoMaxwell/mxpic_EDA
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Programm architecture simplified so that the EDA can now run individually without generation of .gds file

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PotatoMaxwell
2026-06-01 09:19:44 +08:00
parent 78f38d3be7
commit 7cf618fe02
160 changed files with 1640 additions and 11497 deletions
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database/admin/layout/MZM_TX/MZM_TX.svg
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database/admin/layout/MZM_TX/MZM_TX.yml
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# =============================================
# mxPIC Cell/Project Definition File
# =============================================
schema_version: "2.0.0"
kind: cell
coordinate_system: gds_y_up
canvas_size:
width: 5000
height: 5000
project: MZM_TX
name: MZM_TX
type: project
version: "1.0.0"
# 1. External Ports (How this cell connects to the outside world)
pins: []
# 2. Instances (The sub-components dropped onto this canvas)
instances:
Spliter_1x4:
component: Spliter_1x4
x: 330.0
y: -630.0
rotation: 0.0
flip: 0
flop: 0
mirror: false
settings:
length:
MZM_1:
component: Silterra/EMO1_2ML_CU_Al_RDL/composites/Mach_Zender_modulators/MZI_SiN400_Si220_PIN_mod_1310_L1300_QY_202603
x: 750.0
y: -460.0
rotation: 0.0
flip: 0
flop: 0
mirror: false
settings:
length:
EC_1:
component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/edge_couplers/EC_SiN400_1310_0p5dB_L935_A0_QY_202604
x: 0.0
y: -920.0
rotation: 180.0
flip: 0
flop: 0
mirror: false
settings:
length:
elements:
anchor_2:
type: anchor
x: 470.0
y: -840.0
angle: 0.0
pin_number: 1
pitch: 10
layer: WG_CORE
width: 0.5
description: ""
pins:
- name: anchor_2_a1
role: a1
- name: anchor_2_b1
role: b1
# 3. Bundles (Grouped links for multi-bus/parallel routing)
bundles:
output_bus:
routing_type: euler_bend
links:
- from: MZM_1:a1
to: Spliter_1x4:OutUp_io2
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: Spliter_1x4:OutUp_io1
to: MZM_1:a2
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: anchor_2:anchor_2_b1
to: EC_1:a1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: anchor_2:anchor_2_a1
to: Spliter_1x4:Input_io1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
database/admin/layout/MZM_TX/Spliter_1x4.yml
-192
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# =============================================
# mxPIC Cell/Project Definition File
# =============================================
schema_version: "2.0.0"
kind: cell
coordinate_system: gds_y_up
canvas_size:
width: 500
height: 500
project: MZM_TX
name: Spliter_1x4
type: composite
version: "1.0.0"
# 1. External Ports (How this cell connects to the outside world)
pins:
- name: Input_io1
layer: WG_CORE
element: Input
pin: io1
x: 10.0
y: -110.0
angle: 180.0
width: 0.5
- name: OutUp_io1
layer: WG_CORE
element: OutUp
pin: io1
x: 335.0
y: -20.0
angle: 90.0
width: 0.5
- name: OutUp_io2
layer: WG_CORE
element: OutUp
pin: io2
x: 325.0
y: -20.0
angle: 90.0
width: 0.5
- name: port_4_io1
layer: WG_CORE
element: port_4
pin: io1
x: 350.0
y: -180.0
angle: 0.0
width: 0.5
# 2. Instances (The sub-components dropped onto this canvas)
instances:
MMI_2:
component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
x: 90.0
y: -110.0
rotation: 0.0
flip: 0
flop: 0
mirror: false
settings:
length:
MMI_3:
component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
x: 230.0
y: -90.0
rotation: 0.0
flip: 0
flop: 0
mirror: false
settings:
length:
elements:
Input:
type: port
x: 10.0
y: -110.0
angle: 0.0
pin_number: 1
pitch: 10
layer: WG_CORE
width: 0.5
description: ""
pins:
- name: Input_io1
role: io1
OutUp:
type: port
x: 330.0
y: -20.0
angle: -90.0
pin_number: 2
pitch: 10
layer: WG_CORE
width: 0.5
description: ""
pins:
- name: OutUp_io1
role: io1
- name: OutUp_io2
role: io2
port_4:
type: port
x: 350.0
y: -180.0
angle: 180.0
pin_number: 1
pitch: 10
layer: WG_CORE
width: 0.5
description: ""
pins:
- name: port_4_io1
role: io1
anchor_1:
type: anchor
x: 250.0
y: -150.0
angle: 90.0
pin_number: 1
pitch: 10
layer: WG_CORE
width: 0.5
description: ""
pins:
- name: anchor_1_a1
role: a1
- name: anchor_1_b1
role: b1
# 3. Bundles (Grouped links for multi-bus/parallel routing)
bundles:
output_bus:
routing_type: euler_bend
links:
- from: MMI_2:a1
to: Input:Input_io1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: MMI_3:a1
to: MMI_2:b1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: MMI_3:b1
to: OutUp:OutUp_io1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: MMI_3:b1
to: OutUp:OutUp_io2
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: MMI_3:b2
to: OutUp:OutUp_io1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: MMI_2:b2
to: anchor_1:anchor_1_b1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: anchor_1:anchor_1_a1
to: port_4:port_4_io1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
- from: anchor_1:anchor_1_a1
to: anchor_1:anchor_1_b1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend
database/admin/layout/MZM_TX/canvas_1.svg
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database/admin/layout/MZM_TX/.project.json → database/admin/layout/mxpic_project_1/.project.json
+1 -1
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@@ -1,4 +1,4 @@
{
"name": "MZM_TX",
"name": "mxpic_project_1",
"technology": "Silterra/EMO1_2ML_CU_Al_RDL"
}
database/admin/layout/MZM_TX/Spliter_1x4.svg → database/admin/layout/mxpic_project_1/mxpic_project_1.svg
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database/admin/layout/mxpic_project_1/mxpic_project_1.yml
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# =============================================
# mxPIC Cell/Project Definition File
# =============================================
schema_version: "2.0.0"
kind: cell
coordinate_system: gds_y_up
canvas_size:
width: 5000
height: 5000
project: mxpic_project_1
name: mxpic_project_1
type: project
version: "1.0.0"
# 1. External Ports (How this cell connects to the outside world)
pins:
- name: port_io1
layer: WG_CORE
element: port
pin: io1
x: 50.0
y: -150.0
angle: 180.0
width: 0.5
# 2. Instances (The sub-components dropped onto this canvas)
instances:
MMI_1:
component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
x: 557.2
y: -1888.3
rotation: 0.0
flip: 0
flop: 0
mirror: false
settings:
length:
MMI_2:
component: Silterra/EMO1_2ML_CU_Al_RDL/primitives/multimode_interferometers/1x2MMI_1310nm_TE_Silterra_202603_ZKY_v2
x: 689.2
y: -1797.5
rotation: 0.0
flip: 0
flop: 0
mirror: false
settings:
length:
elements:
port:
type: port
x: 50.0
y: -150.0
angle: 180.0
pin_number: 1
pitch: 10
layer: WG_CORE
width: 0.5
description: ""
pins:
- name: port_io1
role: io1
port:
type: port
x: 50.0
y: -150.0
angle: 0.0
pin_number: 1
pitch: 10
layer: WG_CORE
width: 0.5
description: ""
pins:
- name: port_io1
role: io1
# 3. Bundles (Grouped links for multi-bus/parallel routing)
bundles:
output_bus:
routing_type: euler_bend
links:
- from: MMI_1:b1
to: MMI_2:a1
xsection: strip
family: optical
width: 0.45
radius: 10
routing_type: euler_bend